Skip to main content

Manufacturing Testing and Security Countermeasures

  • Chapter
  • First Online:
Hardware Security and Trust

Abstract

Cryptographic algorithms are used to protect sensitive information when the communication medium is not secure. Unfortunately, the hardware implementation of these cryptographic algorithms allows secret key retrieval using different forms of attacks based on the observation of key-related information. Dedicated design for security techniques have been proposed so far, ranging from the development of specific cell libraries to the implementation of extra functions to prevent leakage of useful information and key identification. On the other hand, one can expect high-quality product for secure applications and this expectation requires the development of test solutions for every component of the secure device. However, testing those devices faces a double dilemma: (i) test and, possibly, develop DfT schemes providing high testability, i.e., high signal controllability/observability, while maintaining high security, i.e., without leakage of sensitive information; (ii) provide high security using dedicated design rules while maintaining high testability. This chapter addresses these issues, discusses pros and cons of security-dedicated DfT from both a design and a testability point of view.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 79.99
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 99.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD 139.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

References

  1. Abramovici M, Breuer MA, Firedman AD. Digital system testing and testable design, Revised Printing, IEEE Press; 1990. ISBN 0-7803-1062-4.

    Google Scholar 

  2. Richard A. Wheelus TD, Haverkos KWJ, Integrated circuit memory using fusible links in a scan chain. U.S. Patent US5677917, issued April; 1996.

    Google Scholar 

  3. Bardell PH, McAnney WH, Self-testing of multichip logic modules. In: Proceedings of international test conference; Nov. 1982. p. 200–04.

    Google Scholar 

  4. Schubert A, Anheier W. On random pattern testability of cryptographic VLSI cores. J Elect Test Theory Appl. 2000;16(3):185–92.

    Google Scholar 

  5. Shannon C. A mathematical theory of communication. Bell Syst Tech J. 1948;27(4):379–423.

    Article  MathSciNet  MATH  Google Scholar 

  6. Shannon C. Communication theory of secrecy systems. Bell Syst Tech J. 1949;28(4):656–715.

    Article  MathSciNet  MATH  Google Scholar 

  7. Feistel H. Cryptography and computer privacy. Sci Amer Mag. 1973;228:15–23.

    Article  Google Scholar 

  8. Di Natale G, Doulcier M, Flottes ML, Rouzeyre B. Self-test techniques for crypto-devices. In: IEEE transaction on VLSI systems, vol. 18, Issue 2. p. 1–5, Feb 2010. DOI:10.1109/TVLSI.2008.2010045.

  9. Doulcier M, Flottes ML, Rouzeyre B. AES-based BIST: self- test, test pattern generation and signature analysis. In: Proceedins of 4th IEEE international symposium electron design, test applications (DELTA), 2008. p. 314–21.

    Google Scholar 

  10. Joan D, Vincent R. The design of rinjael, AES—the advanced encryption standard. 2nd ed. New York: Springer.

    Google Scholar 

  11. Recommendation for the Triple Data Encryption Algorithm (TDEA). Block Cipher, Special Publication 800–67, Gaithersburg, MD: National Institude Standards Technology (NIST); 2008.

    Google Scholar 

  12. Karaklajic D, Kneževic M, Verbauwhede I. Low cost built in self test for public key crypto cores. In: Workshop on fault diagnosis and tolerance in cryptography (FDTC). Santa Barbara, CA. 2010. p. 97–103. doi:10.1109/FDTC.2010.12.

  13. da Rolt J, Di Natale G, Flottes ML, Rouzeyre B. Thwarting scan-based attacks on secure-ICs with on-chip comparison. IEEE Trans Very Large Scale Int Syst. 2014;22(4):947–51. doi:10.1109/TVLSI.2013.2257903.

  14. Sudeendra Kumar K, Lodha K, Sahoo SR, Mahapatra KK. On-chip comparison based secure output response compactor for scan-based attack resistance. In: 2015 international conference on VLSI systems, architecture, technology and applications (VLSI-SATA). Bangalore; 2015. p. 1–6. DOI:10.1109/VLSI-SATA.2015.7050467.

  15. Talatule SD, Zode P, Zode P. A secure architecture for the design for testability structures. In: 19th international symposium on VLSI design and test (VDAT). Ahmedabad. 2015:1–6. doi:10.1109/ISVDAT.2015.7208090.

  16. Wu Y, MacDonald P. Testing ASICs with multiple identical cores. IEEE Trans Comput Aided Des Int Circ Syst. 2003;22(3):327–36.

    Article  Google Scholar 

  17. Poehl F, Beck M, Arnold R, Rzeha J, Rabenalt T, Goessel M. On-chip evaluation, compensation and storage of scan diagnosis data. IET Comput Dig Tech. 2007;1(3):207–12.

    Article  Google Scholar 

  18. Paul S, Chakraborty R, Bhunia S. VIm-scan: a low overhead scan design approach for protection of secret key in scan-based secure chips. In: Proceedings of 25th IEEE VLSI test symposium, May 2007. p. 455–60.

    Google Scholar 

  19. Lee J, Tebranipoor M, Plusquellic J. A low-cost solution for protecting IPs against scan-based side-channel attacks. In: Proceedings of 24th IEEE VLSI test symposium, May 2006, p. 1–6.

    Google Scholar 

  20. Novak F, Biasizzo A. Security extension for IEEE Std 1149.1. J Elect Test. 2006;22(3):301–3.

    Google Scholar 

  21. Chiu G-M, Li JC-M. A secure test wrapper design against internal and boundary scan attacks for embedded cores. IEEE Trans Very Large Scale Integr Syst. 2012;20(1):126–34.

    Google Scholar 

  22. Wang X, Zheng Y, Basak A, Bhunia S. IIPS: infrastructure IP for secure SoC design. IEEE Trans on Comput. 2015;64(8):2226–38. doi:10.1109/TC.2014.2360535.

  23. Dworak J, Conroy Z, Crouch A, Potter J. Board security enhancement using new locking SIB-based architectures. In: IEEE international test conference (ITC), WA: Seattle; 2014. p. 1–10. doi:10.1109/TEST.2014.7035355.

  24. Da Rolt J, Di Natale G, Flottes ML, Rouzeyre B. A smart test controller for scan chains in secure circuits. In: Proceedinigs IEEE 19th IOLTS, July 2013. p. 228–9.

    Google Scholar 

  25. Yang B, Wu K, Karri R, Secure scan: a design-for-test architecture for crypto chips. IEEE Trans Comput Aided Des Integr Circ Syst. 2006;25(10):2287–93.

    Google Scholar 

  26. Hely D, Flottes ML, Bancel F, Rouzeyre B, Berard N, Renovell M. Scan design and secure chip [secure IC testing]. In: Proceedings of 10th IEEE IOLTS, July 2004. p. 219–24.

    Google Scholar 

  27. Lee J, Tehranipoor M, Patel C, Plusquellic J. Securing scan design using lock and key technique. In: Proceedings of 20th IEEE international symposium DFT VLSI system, Oct. 2005. p. 51–62.

    Google Scholar 

  28. Fujiwara H, Fujiwara K. Strongly secure scan design using generalized feed forward shift registers. IEICE Trans Inf Syst. 2015;E98-D(10):1852–55.

    Google Scholar 

  29. Atobe Y, Shi Y, Yanagisawa M, Togawa N. Dynamically changeable secure scan architecture against scan-based side channel attack. In: International SoC design conference (ISOCC). Jeju Island; 2012. p. 155–8. doi:10.1109/ISOCC.2012.6407063.

  30. Ali SS, Saeed SM, Sinanoglu O, Karri R. Novel test-mode-only scan attack and countermeasure for compression-based scan architectures. In: IEEE transactions on computer-aided design of integrated circuits and systems. 2015;34(5):808–21. doi:10.1109/TCAD.2015.2398423.

  31. Saeed SM, Ali SS, Sinanoglu O, Karri R. Test-mode-only scan attack and countermeasure for contemporary scan architectures. In: IEEE international test conference (ITC), Seattle, WA; 2014. p. 1–8. doi:10.1109/TEST.2014.7035357.

  32. Hely D, Bancel F, Flottes ML, Rouzeyre B: Secure scan techniques: a comparison. In: Proceedings 12th IEEE ISOLT, Jan. 2006. p. 119–24.

    Google Scholar 

  33. http://www.cadence.com/products/ld/rtl_compiler/pages/default.aspx

  34. http://www.synopsys.com/Tools/Implementation/RTLSynthesis/DesignCompiler/

  35. https://www.mentor.com/products/silicon-yield/products/scan

  36. http://www.synopsys.com/Tools/Implementation/RTLSynthesis/Test/Pages/TetraMAXATPG.aspx

  37. https://www.mentor.com/products/silicon-yield/products/testkompress/

  38. http://www.cadence.com/products/di/edi_system/pages/default.aspx

  39. Yang B, Wu K, Karri R. Scan based side channel attack on dedicated hardware implementations of Data Encryption Standard. In: International test conference, 2004. p. 339–44.

    Google Scholar 

  40. Nara R et al. RScan-based attack against elliptic curve cryptosystems. In: ASP-DAC, 2010. p. 407–12.

    Google Scholar 

  41. Darolt J, Di Natale G, Flottes ML, Rouzeyre B. Are advanced DfT structures sufficient for preventing scan-attacks?. In: VLSI test symposium, 2012. p. 246–51

    Google Scholar 

  42. Hely D, Bancel F, Flottes M-L, Rouzeyre B. Securing scan control in crypto chips. JETTA. 2007;23(5):457–64.

    Google Scholar 

  43. Pugliesi-Conti PH. Circuit for securing scan chain data, patent filed, March 25, 2011, Publication number: 20120246528.

    Google Scholar 

  44. van de Goor AJ. Testing semiconductor memories: theory and practice. John Wiley and Sons, 1991.

    Google Scholar 

  45. Zarrineh K, Upadhyaya SJ, Chakravarty S. A new framework for generating optimal march tests for memory arrays. In: IEEE international test conference, 1998. p. 73–82.

    Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Giorgio Di Natale .

Editor information

Editors and Affiliations

Rights and permissions

Reprints and permissions

Copyright information

© 2017 Springer International Publishing Switzerland

About this chapter

Cite this chapter

Di Natale, G., Flottes, ML., Rouzeyre, B., Pugliesi-Conti, PH. (2017). Manufacturing Testing and Security Countermeasures. In: Sklavos, N., Chaves, R., Di Natale, G., Regazzoni, F. (eds) Hardware Security and Trust. Springer, Cham. https://doi.org/10.1007/978-3-319-44318-8_7

Download citation

  • DOI: https://doi.org/10.1007/978-3-319-44318-8_7

  • Published:

  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-319-44316-4

  • Online ISBN: 978-3-319-44318-8

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics