Abstract
This chapter gives an extensive description of ring oscillators (ROs) implemented on Xilinx FPGA technology, aiming at providing a basic primitive to define physically unclonable functions based on ROs and illustrating, through detailed analyses, frequency distributions. As for the implementation, we detail in the chapter any step required to implement a RO and measure its frequency. In particular, we illustrate how to accomplish such operation by means of Xilinx ChipScope. Furthermore, we show main design parameters, such as the number of stages, of the RO and how they impact on the frequency characterization. At the end, we provide other characterization by means of dynamic parameters variations, such as temperature and aging effects.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
Amouri A, Bruguier F, Kiamehr S, Benoit P, Torres L, Tahoori M. Aging effects in fpgas: an experimental analysis. In: 2014 24th international conference on Field Programmable Logic and Applications (FPL); 2014. p. 1–4.
Anderson JH. A puf design for secure FPGA-based embedded systems. In: Proceedings of the 2010 Asia and South Pacific design automation conference. IEEE Press; 2010. p. 1–6.
Barbareschi M, Bagnasco P, Mazzeo A. Supply voltage variation impact on Anderson PUF quality. In: 2015 10th international conference on Design and Technology of Integrated Systems in Nanoscale Era (DTIS). IEEE; 2015. p. 1–6.
Barbareschi M, Battista E, Mazzeo A, Mazzocca N. Testing 90 nm microcontroller SRAM PUF quality. In: 2015 10th international conference on Design and Technology of Integrated Systems in Nanoscale Era (DTIS). IEEE; 2015. p. 1–6.
Gassend B, Clarke D, Van Dijk M, Devadas S. Silicon physical random functions. In: Proceedings of the 9th ACM conference on computer and communications security. ACM; 2002. p. 148–60.
Holcomb DE, Burleson WP, Fu K. Power-up SRAM state as an identifying fingerprint and source of true random numbers. IEEE Trans Comput. 2009;58(9):1198–210.
Kumar SS, Guajardo J, Maes R, Schrijen G-J, Tuyls P. The butterfly PUF protecting IP on every FPGA. In: IEEE international workshop on hardware-oriented security and trust, 2008. HOST 2008. IEEE; 2008. p. 67–70.
Lim D, Lee JW, Gassend B, Suh GE, Van Dijk M, Devadas S. Extracting secret keys from integrated circuits. IEEE Trans Very Large Scale Integr VLSI Syst. 2005;13(10):1200–5.
Lorenz D, Georgakos G, Schlichtmann U. Aging analysis of circuit timing considering NBTI and HCI. In: 15th IEEE international on-line testing symposium, 2009. IOLTS 2009. IEEE; 2009. p. 3–8.
Maes R, Verbauwhede I. Physically unclonable functions: a study on the state of the art and future research directions. In: Towards hardware-intrinsic security. Springer; 2010. p. 3–37.
Maiti A, Casarona J, McHale L, Schaumont P. A large scale characterization of RO-PUF. In: 2010 IEEE international symposium on Hardware-Oriented Security and Trust (HOST). IEEE; 2010. p. 94–9.
Maiti A, Schaumont P. Improving the quality of a physical unclonable function using configurable ring oscillators. In: International conference on field programmable logic and applications, 2009. FPL 2009. IEEE; 2009. p. 703–7.
Maiti A, Schaumont P. Improved ring oscillator PUF: an FPGA-friendly secure primitive. J Cryptol. 2011;24(2):375–97.
Merli D, Stumpf F, Eckert C. Improving the quality of ring oscillator PUFs on FPGAs. In: Proceedings of the 5th workshop on embedded systems security. ACM; 2010. p. 9.
Qu G, Yin C-E. Temperature-aware cooperative ring oscillator PUF. In: IEEE international workshop on hardware-oriented security and trust, 2009. HOST’09. IEEE; 2009. p. 36–42.
Skorobogatov S, Woods C. Breakthrough silicon scanning discovers backdoor in military chip. Springer; 2012.
Suh GE, Devadas S. Physical unclonable functions for device authentication and secret key generation. In: Proceedings of the 44th annual design automation conference. ACM; 2007. p. 9–14.
van der Leest V, Schrijen G-J, Handschuh H, Tuyls P. Hardware intrinsic security from D flip-flops. In: Proceedings of the fifth ACM workshop on scalable trusted computing. ACM; 2010. p. 53–62.
Vatajelu EI, Di Natale G, Barbareschi M, Torres L, Indaco M, Prinetto P. Spin-transfer torque magnetic random access memory (STT-MRAM). ACM J Emer Technol Comput Syst JETC. 2015.
Xilinx. Spartan-6 family overview. Available at http://www.xilinx.com/support/documentation/data_sheets/ds160.pdf.
Xilinx. Spartan-6 FPGA configurable logic block. Available at http://www.xilinx.com/support/documentation/user_guides/ug384.pdf.
Xilinx. Spartan-6 FPGA data sheet: DC and switching characteristics. Available at http://www.xilinx.com/support/documentation/data_sheets/ds162.pdf.
Xin X, Kaps J-P, Gaj K. A configurable ring-oscillator-based PUF for xilinx FPGAs. In: 2011 14th euromicro conference on Digital System Design (DSD). IEEE; 2011. p. 651–7.
Yin C-ED, Qu G. LISA: maximizing RO PUF’s secret extraction. In: 2010 IEEE international symposium on Hardware-Oriented Security and Trust (HOST). IEEE; 2010. p. 100–5.
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2017 Springer International Publishing Switzerland
About this chapter
Cite this chapter
Barbareschi, M., Di Natale, G., Torres, L. (2017). Implementation and Analysis of Ring Oscillator Circuits on Xilinx FPGAs. In: Sklavos, N., Chaves, R., Di Natale, G., Regazzoni, F. (eds) Hardware Security and Trust. Springer, Cham. https://doi.org/10.1007/978-3-319-44318-8_12
Download citation
DOI: https://doi.org/10.1007/978-3-319-44318-8_12
Published:
Publisher Name: Springer, Cham
Print ISBN: 978-3-319-44316-4
Online ISBN: 978-3-319-44318-8
eBook Packages: EngineeringEngineering (R0)