Abstract
The strong interaction between Electronic Design Automation (EDA) tools and Complementary Metal-Oxide Semiconductor (CMOS) technology contributed substantially to the advancement of modern digital electronics.
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References
G.E. Moore, Cramming more components onto integrated circuits. Proc. IEEE 86(1), 82–85 (1998)
D. Hisamoto et al., FinFET-a self-aligned double-gate MOSFET scalable to 20 nm. IEEE Trans. Electron Devices 47(12), 2320–2325 (2000)
M. Bohr, Technology Insight: 14 nm Process Technology—Opening New Horizons, Intel Developer Forum 2014, San Francisco
G. De Micheli, Synthesis and Optimization of Digital Circuits (McGraw-Hill Higher Education, United States, 1994)
J. Buchanan, The GDSII Stream Format, June 1996
S. Brown et al., Field-Programmable Gate Arrays, vol. 180 (Springer Science & Business Media, Heidelberg, 2012)
A. Kahng et al., VLSI Physical Design: From Graph Partitioning to Timing Closure (Springer Science & Business Media, Heidelberg, 2011)
E. Clarke, J.M. Wing, Formal methods: state of the art and future directions. ACM Comput. Surv. (CSUR) 28(4), 626–643 (1996)
F. Krohm, The Use of Random Simulation in Formal Verification. IEEE International Conference on Computer Design (1996)
R.E. Bryant, Graph-based algorithms for Boolean function manipulation. IEEE Trans. Comput. C-35(8), 677–691 (1986)
A. Biere et al. (ed.), Handbook of Satisfiability, vol. 185 (IOS Press, Amsterdam, 2009)
R.L. Rudell, A. Sangiovanni-Vincentelli, Multiple-valued minimization for PLA optimization. IEEE Trans. CAD 6(5), 727–750 (1987)
R.K. Brayton, G.D. Hachtel, A.L. Sangiovanni-Vincentelli, Multilevel logic synthesis. Proc. IEEE 78(2), 264–300 (1990)
L. Amaru, P.-E. Gaillardon, G. De Micheli, Majority-Inverter Graph: A Novel Data-Structure and Algorithms for Efficient Logic Optimization. Design Automation Conference (DAC) (CA, USA, San Francisco, 2014)
M. Ciesielski, C. Yu, W. Brown, D. Liu, A. Rossi, Verification of Gate-level Arithmetic Circuits by Function Extraction. ACM Design Automation Conference (DAC-2015) (2015)
L. Amaru, P.-E. Gaillardon, R. Wille, G. De Micheli, Exploiting Inherent Characteristics of Reversible Circuits for Faster Combinational Equivalence Checking, DATE’16
K. Bernstein et al., Device and architecture outlook for beyond CMOS switches. Proc. IEEE 98(12), 2169–2184 (2010)
T. Ernst, Controlling the polarity of silicon nanowire transistors. Science 340, 1414 (2013)
Y.-M Lin et al., High-performance carbon nanotube field-effect transistor with tunable polarities. IEEE Trans. Nanotechnol. 4(5), 481–489 (2005)
H. Yang et al., Graphene barristor, a triode device with a gate-controlled Schottky barrier. Science 336, 1140 (2012)
S.-L. Li et al., Complementary-like graphene logic gates controlled by electrostatic doping. Small 7(11), 1552–1556 (2011)
S. Iba et al., Control of threshold voltage of organic field-effect transistors with double-gate structures. Appl. Phys. Lett. 87(2), 023509 (2005)
D. Lee et al., Combinational logic design using six-terminal NEM relays. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 32(5), 653–666 (2013)
M. Spencer et al., Demonstration of integrated micro-electro-mechanical relay circuits for VLSI applications. IEEE J. Solid-State Circuits 46(1), 308–320 (2011)
T. Toffoli, Reversible computing, in Automata, Languages and Programming, ed. by W. de Bakker, J. van Leeuwen (Springer, Heidelberg, 1980), p. 632. (Technical Memo MIT/LCS/TM-151, MIT Lab. for Comput. Sci)
T. Schneider et al., Realization of spin-wave logic gates. Appl. Phys. Lett. 92(2), 022505 (2008)
A. Khitun, K.L. Wang, Nano scale computational architectures with spin wave bus. Superlattices Microstruct. 38(3), 184–200 (2005)
A. Khitun et al., Non-volatile magnonic logic circuits engineering. J. Appl. Phys. 110, 034306 (2011)
E. Linn, R. Rosezin, C. Kügeler, R. Waser, Complementary resistive switches for passive nanocrossbar memories. Nat. Mater. 9, 403 (2010)
E. Linn, R. Rosezin, S. Tappertzhofen, U. Böttger, R. Waser, Beyond von Neumann–logic operations in passive crossbar arrays alongside memory operations. Nanotechnology 23(305205) (2012)
S. Miryala et al., Exploiting the Expressive Power of Graphene Reconfigurable Gates via Post-Synthesis Optimization, in Proceedings of the GLVSLI’15
I. Amlani et al., Digital logic gate using quantum-dot cellular automata. Science 284(5412), 289–291 (1999)
L. Wei et al., Three-input majority logic gate and multiple input logic circuit based on DNA strand displacement. Nano Lett. 13(6), 2980–2988 (2013)
L. Amaru, P.-E. Gaillardon, S. Mitra, G. De Micheli, New logic synthesis as nanotechnology enabler, in Proceedings of the IEEE (2015)
A. Mishchenko, S. Chatterjee, R.K. Brayton, DAG-aware AIG rewriting a fresh look at combinational logic synthesis, in Proceedings of the 43rd Annual Design Automation Conference, pp. 532–535 (2006)
A. Mishchenko et al., Delay optimization using SOP balancing, in Proceedings of the ICCAD (2011)
A. Mishchenko at al., Using simulation and satisfiability to compute flexibilities in Boolean networks. IEEE TCAD 25(5), 743–755 (2006)
O. Coudert, J.C. Madre, A unified framework for the formal verification of sequential circuits. Proceedings of the ICCAD (1990)
O. Coudert, C. Berthet, J.C. Madre, Verification of sequential machines using Boolean functional vectors, in Proceedings of the International Workshop on Applied Formal Methods for Correct VLSI Design (1989)
A. Mishchenko et al., Improvements to combinational equivalence checking. IEEE/ACM International Conference on Computer-Aided Design, ICCAD’06 (2006)
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Amaru, L.G. (2017). Introduction. In: New Data Structures and Algorithms for Logic Synthesis and Verification. Springer, Cham. https://doi.org/10.1007/978-3-319-43174-1_1
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DOI: https://doi.org/10.1007/978-3-319-43174-1_1
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