Abstract
The AXIOM hardware/software platform aims at bringing easy programmability on top of a cluster of processors by using a fast interconnect and FPGA as a basis for building a scalable embedded system. The Smart Home is one of the key scenarios in which AXIOM could be useful for the Internet-of-Things (IoT). In Smart Homes, everything is linked to the flow of information that from the “on the field” devices needs to arrive to the cloud servers. The information sensed in the environment will not be transmitted as is to the higher layers, but is somehow interpreted to provide a synthetic light-weight representation of the environment. In such a scenario, it is then clear that there is a need for peripheral nodes as well as intermediate gateways which needs to be able to perform high-performance computational loads. AXIOM provides the possibility of designing a cluster of low-power/low-budget boards, which could be packed inside a “high-performance embedded low-cost product.” The AXIOM boards are heterogeneous, thus allowing for even greater diversity which is needed in those kind of IoT scenarios. The cluster itself can then be integrated inside the IoT architectures as “computational-power node,” which could be the center of a distributed intelligence near the edges of the IoT network.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Notes
- 1.
Source to HDL Xilinx tool.
References
W. Ahmed, M. Shafique, L. Bauer, J. Karlsruhe, Adaptive resource management for simultaneous multitasking in mixed-grained reconfigurable multi-core processors, in 2011 Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), pp. 365–374 (2011)
C. Alvarez et al., The AXIOM software layers, in Digital System Design (DSD) (2015)
E. Argollo, A. Falcón, P. Faraboschi, M. Monchiero, D. Ortega, COTSon: infrastructure for full system simulation. SIGOPS Oper. Syst. Rev. 43 (1), 52–61 (2009). doi:http://doi.acm.org/10.1145/1496909.1496921
E. Ayguade, R.M. Badia, D. Cabrera, A. Duran, M. Gonzalez, F. Igual, D. Jimenez, J. Labarta, X. Martorell, R. Mayo, J.M. Perez, E.S. Quintana-Orti, A proposal to extend the openmp tasking model for heterogeneous architectures, in International Workshop on OpenMP (IWOMP), vol. 5568, pp. 154–167 (2009)
M. Banzi, Getting Started with Arduino (Make Books - Imprint of: O’Reilly Media, Sebastopol, CA, 2008)
J. Bueno, L. Martinell, A. Duran, M. Farreras, X. Martorell, R. Badia, E. Ayguade, J. Labarta, Productive cluster programming with OmpSs, in Euro-Par 2011 Parallel Processing, pp. 555–566 (2011)
J. Clemente, V. Rana, D. Sciuto, I. Beretta, D. Atienza, A hybrid mapping-scheduling technique for dynamically reconfigurable hardware, in 2011 International Conference on Field Programmable Logic and Applications (FPL), pp. 177–180 (2011). doi:10.1109/FPL.2011.40
D.J. Cook, A.S. Crandall, B.L. Thomas, N.C. Krishnan, CASAS: a smart home in a box. Computer 46 (7), 62–69 (2013). doi:http://doi.ieeecomputersociety.org/10.1109/MC.2012.328
R. Ferrer, S. Royuela, D. Caballero, A. Duran, X. Martorell, E. Ayguade, Mercurium: Design decisions for a S2S compiler, in Proceedings of the Cetus Users and Compiler Infrastructure Workshop in conjunction with PACT (2011)
R. Giorgi, Accelerating haskell on a dataflow architecture: a case study including transactional memory, in Computer Engineering and Applications (CEA), pp. 91–100 (2015)
R. Giorgi, Scalable embedded systems: towards the convergence of high-performance and embedded computing, in Proceedings of the 13th IEEE/IFIP International Conference on Embedded and Ubiquitous Computing (EUC 2015) (2015)
R. Giorgi, P. Faraboschi, An introduction to DF-Threads and their execution model, in IEEE MPP, pp. 60–65 (2014). doi:10.1109/SBAC-PADW.2014.30
R. Giorgi, A. Scionti, A scalable thread scheduling co-processor based on data-flow principles. ELSEVIER Futur. Gener. Comput. Syst. 53, 100–108 (2015). doi:10.1016/j.future. 2014.12.014. http://www.sciencedirect.com/science/article/pii/S0167739X1400274X
R. Giorgi et al., TERAFLUX: harnessing dataflow in next generation teradevices. Microprocess. Microsyst. 38 (8, Part B), 976–990 (2014)
M. Herlihy, J.E.B. Moss, Transactional memory: architectural support for lock-free data structures, in Proceedings of the 20th Annual International Symposium on Computer Architecture, ISCA ’93 (ACM, New York, 1993), pp. 289–300. doi:10.1145/165123.165164
Intel: Could Smart Homes Be as Commonplace as Smartphones by 2025. http://download.intel.com/newsroom/kits/iot/pdfs/IntelSmartHomeSurveyBackgrounder.pdf. Last accessed on Feb 2016
N. Komninos, E. Philippou, A. Pitsillides, Survey in smart grid and smart home security: issues, challenges and countermeasures. IEEE Commun. Surv. Tutor. 16 (4), 1933–1954 (2014). doi:10.1109/COMST.2014.2320093
S. Lyberis, G. Kalokerinos, M. Lygerakis, V. Papaefstathiou, D. Tsaliagkos, M. Katevenis, D. Pnevmatikatos, D. Nikolopoulos, Formic: cost-efficient and scalable prototyping of manycore architectures, in 2012 IEEE 20th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM) (IEEE, New York, 2012), pp. 61–64
E. Palazzetti, Getting Started with UDOO (Packt Publishing, Birmingham, 2015)
V. Pillet, J. Labarta, T. Cortes, S. Girona, PARAVER: a tool to visualise and analyze parallel code, in Proceedings of WoTUG-18: Transputer and Occam Developments (1995)
N. Puzovic, S. McKee, R. Eres, A. Zaks, P. Gai, S. Wong, R. Giorgi, A multi-pronged approach to benchmark characterization, in IEEE CLUSTER, pp. 1–4 (2010). doi:10.1109/ CLUSTERWKSP.2010.5613090
S. Ray, Y. Jin, A. Raychowdhury, The changing computing paradigm with internet of things: a tutorial introduction. IEEE Des. Test 33 (2), 76–96 (2016). doi:10.1109/MDAT.2016.2526612
A. Scionti, S. Kavvadias, R. Giorgi, Dynamic power reduction in self-adaptive embedded systems through benchmark analysis, in IEEE Mediterranean Conference on Embedded Computing (MECO), pp. 62–65 (2014)
D. Theodoropoulos et al., The AXIOM project (agile, extensible, fast I/O module), in SAMOS (2015)
O. Vermesan, P. Friess, P. Guillemin, S. Gusmeroli, H. Sundmaeker, A. Bassi, I.S. Jubert, M. Mazura, M. Harrison et al. Internet of things strategic research roadmap, in Internet of Things-Global Technological and Societal Trends, pp. 9–52 (2011)
S. Weis, A. Garbade, J. Wolf, B. Fechner, A. Mendelson, R. Giorgi, T. Ungerer, A fault detection and recovery architecture for a teradevice dataflow system, in, IEEE Design for Manufacturability (DFM), pp. 38–44 (2011)
S. Weis et al., Architectural support for fault tolerance in a teradevice dataflow system. Springer Int. J. Parallel Prog. 44 (2), 208–232 (2016)
Xilinx Inc.: Xilinx UltraScale Architecture, http://www.xilinx.com/support/documentation/white_papers/wp435-Xilinx-UltraScale.pdf. Last accessed on Feb 2016
Xilinx Inc.: Zynq Series, http://www.xilinx.com/content/xilinx/en/products/silicon-devices/soc/zynq-7000.html. Last accessed on Feb 2016
Acknowledgements
We thankfully acknowledge the support of the European Union H2020 program through the AXIOM project (grant ICT-01-2014 GA 645496), the Spanish Government, through the Severo Ochoa program (grant SEV-2011-00067) the Spanish Ministry of Science and Technology (TIN2012-34557), and the Generalitat de Catalunya (MPEXPAR, 2014-SGR-1051).
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2017 Springer International Publishing Switzerland
About this chapter
Cite this chapter
Giorgi, R., Bettin, N., Gai, P., Martorell, X., Rizzo, A. (2017). AXIOM: A Flexible Platform for the Smart Home. In: Keramidas, G., Voros, N., Hübner, M. (eds) Components and Services for IoT Platforms. Springer, Cham. https://doi.org/10.1007/978-3-319-42304-3_3
Download citation
DOI: https://doi.org/10.1007/978-3-319-42304-3_3
Published:
Publisher Name: Springer, Cham
Print ISBN: 978-3-319-42302-9
Online ISBN: 978-3-319-42304-3
eBook Packages: EngineeringEngineering (R0)