Abstract
This paper describes a novel technique to speed up the reconfiguration for the VLSI arrays. We propose an efficient algorithm based on A-star algorithm for accelerating reconfiguration of the power efficient VLSI processor subarrays to meet the real-time constraints and lower power consumption of the embedded systems. The proposed algorithm treats the problem of constructing a local optimal logical column that has the minimum number of long interconnects as a shortest path problem. Then the local optimal column can be constructed by utilizing A-star algorithm with appropriate heuristic strategy. The proposed algorithm greatly reduces the number of visits to the fault-free PEs for constructing a local optimal logical column and effectively decreases the reconfiguration running time. Experimental results show that the computation time can be improved by more than 38.64 % for a \(128 \times 128\) host array with fault density of 20 %, without loss of harvest.
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Acknowledgments
This work is supported by the National Natural Science Foundation of China under grant No. 61262008, 61363030, 61562015, U1501252 and 61572146, the High Level Innovation Team of Guangxi Colleges and Universities and Outstanding Scholars Fund, Guangxi Natural Science Foundation of China under grant No. 2014GXNSFAA118365, 2015GXNSFDA139038, Innovation Project of GUET Graduate Education No. YJCXS201537, Guangxi Key Laboratory of Trusted Software Focus Fund, Program for Innovative Research Team of Guilin University of Electronic Technology.
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Qian, J., Zhou, Z., Zhao, L., Gu, T. (2016). An Improved Reconfiguration Algorithm for VLSI Arrays with A-Star. In: Gervasi, O., et al. Computational Science and Its Applications – ICCSA 2016. ICCSA 2016. Lecture Notes in Computer Science(), vol 9787. Springer, Cham. https://doi.org/10.1007/978-3-319-42108-7_25
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DOI: https://doi.org/10.1007/978-3-319-42108-7_25
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