Abstract
This article reviews the application and the requirements of Sigma-Delta ADCs with improved interferer robustness. While most power efficient state-of-the-art architectures for Sigma-Delta ADCs are based on forward compensated loop filters, these architectures are known to feature gain in their signal transfer function at out-of-band frequencies. In applications, where interferer and blocker signals are present outside the band of interest, gain at these frequencies consequently increases the required dynamic range or the necessary pre-processing complexity, e.g. within the preceding filter stages. More recently, increasing attention was dedicated to improved signal transfer functions of Sigma-Delta ADC’s, such that—by intrinsically attenuating the interferers within the Sigma-Delta loop filter—pre-processing stages can be relaxed or even omitted, and the dynamic range can be reduced. In this contribution, the state-of-the-art of Sigma-Delta ADCs is reviewed with respect to interferer robustness from system level on.
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References
J. de la Rosa, Sigma-delta modulators: tutorial overview, design guide, and state-of-the-art survey. IEEE Trans. Circuits Syst I Regul. Pap. 58 (1), 1–21 (2011)
J. de la Rosa, R. Schreier, K.-P. Pun, S. Pavan, Next-generation delta-sigma converters: trends and perspectives. IEEE J. Emerging Sel. Top. Circuits Syst. 5 (4), 484–499 (2015)
R. Saad, D. Aristizabal-Ramirez, S. Hoyos, Sensitivity analysis of continuous-time \(\varDelta \varSigma\) ADCs to out-of-band blockers in future SAW-less multi-standard wireless receivers. IEEE Trans. Circuits Syst. I Regul. Pap. 59 (9), 1894–1905 (2012)
M. Andersson, M. Anderson, L. Sundstrom, S. Mattisson, P. Andreani, A filtering \(\varDelta \varSigma\) ADC for LTE and beyond. IEEE J. Solid State Circuits 49 (7), 1535–1547 (2014)
R. Ritter, M. Ortmanns, Continuous-time delta-sigma ADCs with improved interferer rejection. IEEE J. Emerging Sel. Top. Circuits Syst. 5 (4), 500–513 (2015)
R. Ritter, Delta-Sigma modulators with enhanced interferer cancellation in receiver applications. Ph.D. dissertation, University of Ulm (2016)
K. Kim, Silicon technologies and solutions for the data-driven world, in 2015 IEEE International Solid- State Circuits Conference - (ISSCC) (2015), pp. 1–7
M. Keller, A. Buhmann, J. Sauerbrey, M. Ortmanns, Y. Manoli, A comparative study on excess-loop-delay compensation techniques for continuous-time sigma-delta modulators. IEEE Trans. Circuits Syst. I Regul. Pap. 55 (11), 3480–3487 (2008)
K. Philips, P. Nuijten, R. Roovers, A. van Roermund, F. Chavero, M. Pallares, A. Torralba, A continuous-time sigma delta ADC with increased immunity to interferers. IEEE J. Solid State Circuits 39 (12), 2170–2178 (2004)
J. De Maeyer, J. Raman, P. Rombouts, L. Weyten, Controlled behaviour of STF in CT \(\varSigma \varDelta\) modulators. Electron. Lett. 41 (16), 19–20 (2005)
M. Ranjbar, O. Oliaei, Continuous-time feedforward SD modulators with robust lowpass STF. Electron. Lett. 43 (24), 1340–1341 (2007)
M. Sosio, A. Liscidini, R. Castello, F. De Bernardinis, A complete DVB-T/ATSC tuner analog base-band implemented with a single filtering ADC, in 2011 Proceedings of the ESSCIRC (ESSCIRC) (2011), pp. 391–394
R. Rajan, S. Pavan, Design techniques for continuous-time \(\varDelta \varSigma\) modulators with embedded active filtering. IEEE J. Solid State Circuits 49 (10), 2187–2198 (2014)
R. Ritter, J. Kauffman, J. Becker, M. Ortmanns, A 10MHz bandwidth, 70dB SNDR continuous time delta-sigma modulator with digitally improved reconfigurable blocker rejection. IEEE J. Solid State Circuits, to appear in 2016
J. Mitola, Software radio architecture: a mathematical perspective. IEEE J. Select. Areas Commun. 17 (4), 514–538 (1999)
A. Abidi, The path to the software-defined radio receiver. IEEE J. Solid State Circuits 42 (5), 954–966 (2007)
H. Shibata, R. Schreier, W. Yang, A. Shaikh, D. Paterson, T. Caldwell, D. Alldred, P.W. Lai, A DC-to-1 GHz tunable RF \(\varDelta \varSigma\) ADC achieving DR = 74 dB and BW = 150 MHz at f0 = 450 MHz using 550 mW. IEEE J. Solid State Circuits 47 (12), 2888–2897 (2012)
H. Chae, J. Jeong, G. Manganaro, M. Flynn, A 12mW low-power continuous-time bandpass \(\varDelta \varSigma\) modulator with 58dB SNDR and 24MHz bandwidth at 200MHz IF, in 2012 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC) (2012), pp. 148–150
J. Harrison, M. Nesselroth, R. Mamuad, A. Behzad, A. Adams, S. Avery, An LC bandpass \(\varDelta \varSigma\) adc with 70dB SNDR over 20MHz bandwidth using CMOS DACs, in 2012 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC) (2012), pp. 146–148
B. Murmann, ADC performance survey 1997–2015. Available: http://web.stanford.edu/∼murmann/adcsurvey.html
M. Englund, K. Ostman, O. Viitala, M. Kaltiokallio, K. Stadius, K. Koli, J. Ryynanen, A programmable 0.7-2.7 GHz direct \(\varDelta \varSigma\) receiver in 40 nm CMOS. IEEE J. Solid State Circuits 50 (3), 644–655 (2015)
P. Chopp, A. Hamoui, A 1-V 13-mW single-path frequency-trans-lating \(\varDelta \varSigma\) modulator with 55-dB SNDR and 4-MHz bandwidth at 225 MHz. IEEE J. Solid State Circuits 48 (2), 473–486 (2013)
ETSI, LTE; Evolved Universal Terrestrial Radio Access (E-UTRA); User Equipment (UE) radio transmission and reception (Release 11), 3GPP TS 36.101, 04 2013, v11.4.0
C.-Y. Ho, C. Liu, C.-L. Lo, H.-C. Tsai, T.-C. Wang, Y.-H. Lin, A 4.5mW CT self-coupled \(\varDelta \varSigma\) modulator with 2.2MHz BW and 90.4dB SNDR using residual ELD compensation, in 2015 IEEE International Solid- State Circuits Conference - (ISSCC) (2015), pp. 1–3
Y.-S. Shu, J.-Y. Tsai, P. Chen, T.-Y. Lo, P.-C. Chiu, A 28fJ/conv-step CT \(\varDelta \varSigma\) modulator with 78dB DR and 18MHz BW in 28nm CMOS using a highly digital multibit quantizer, in 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC) (2013), pp. 268–269
H. Geddada, C.-J. Park, H.-J. Jeon, J. Silva-Martinez, A. Karsilayan, D. Garrity, Design techniques to improve blocker tolerance of continuous-time \(\varDelta \varSigma\) ADCs. IEEE Trans. Very Large Scale Integr. Syst. 23 (1), 54–67 (2015)
R. Schreier, G. Temes, Understanding Delta-Sigma Data Converters (Wiley, New York, 2004)
R. Adams, K. Nguyen, A 113dB SNR oversampling DAC with segmented noise-shaped scrambling. IEEE J. Solid State Circuits 33 (12), 1871–1878 (1998)
M. Ortmanns, F. Gerfers, Y. Manoli, A continuous-time \(\varSigma \varDelta\) modulator with reduced sensitivity to clock jitter through SCR feedback. IEEE Trans. Circuits Syst. I Regul. Pap. 52 (5), 875–884 (2005)
N. Beilleau, H. Aboushady, F. Montaudon, A. Cathelin, A 1.3V 26mW 3.2GS/s undersampled LC bandpass \(\varDelta \varSigma\) ADC for a SDR ISM-band receiver in 130nm CMOS, in 2009 IEEE Radio Frequency Integrated Circuits Symposium. RFIC 2009 (2009), pp. 383–386
O. Oliaei, Sigma-delta modulator with spectrally shaped feedback. IEEE Trans. Circuits Syst. II Analog Digit. Signal Process. 50 (9), 518–530 (2003)
P. Shettigar, S. Pavan, Design techniques for wideband single-bit continuous-time \(\varDelta \varSigma\) modulators with FIR feedback DACs. IEEE J. Solid State Circuits 47 (12), 2865–2879 (2012)
M. Ortmanns, F. Gerfers, Y. Manoli, Fundamental limits of jitter insensitivity in discrete and continuous-time sigma delta modulators, in Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS ’03, vol. 1 (2003), pp. I–I
R. Saad, S. Hoyos, Sensitivity analysis of pulse-width jitter induced noise in continuous-time delta-sigma modulators to out-of-band blockers in wireless receivers, in 2011 IEEE International Symposium on Circuits and Systems (ISCAS) (2011), pp. 1636–1639
F. Munoz, K. Philips, A. Torralba, A 4.7mW 89.5dB DR CT complex \(\varDelta \varSigma\) ADC with built-in LPF, in 2005 IEEE International Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC, vol. 1 (2005), pp. 500–613
S. Loeda, J. Harrison, F. Pourchet, A. Adams, A 10/20/30/40 MHz feed-forward FIR DAC continuous-time \(\varDelta \varSigma\) ADC with robust blocker performance for radio receivers, in 2015 Symposium on VLSI Circuits (VLSI Circuits) (2015), pp. C262–C263
T. Brueckner, C. Zorny, W. Mathisy, M. Ortmanns, A single DAC CT sigma-delta modulator with butterworth STF characteristic, in 2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS) (2011), pp. 1–4
M. Ranjbar, O. Oliaei, R. Jackson, A robust STF 6mW CT \(\varDelta \varSigma\) modulator with 76dB dynamic range and 5Mhz bandwidth, in 2010 IEEE Custom Integrated Circuits Conference (CICC) (2010), pp. 1–4
R. Ritter, M. Lorenz, M. Ortmanns, Anti-aliasing filter improvement in continuous-time feedback sigma-delta modulators. 2015 IEEE International Symposium on Circuits and Systems (ISCAS) (2015), pp. 325–328
M. Sosio, A. Liscidini, R. Castello, A 2G/3G cellular analog baseband based on a filtering ADC. IEEE Trans. Circuits Syst. II Express Briefs 59 (4), 214–218 (2012)
R. Ritter, P. Torta, L. Dorrer, A. Di Giandomenico, S. Herzinger, M. Ortmanns, A multimode CT \(\varDelta \varSigma\)-modulator with a reconfigurable digital feedback filter for semi-digital blocker/interferer rejection, in 2015 - 41st European Solid-State Circuits Conference (ESSCIRC) (2015), pp. 225–228
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Ritter, R., Chi, J., Ortmanns, M. (2017). Sigma-Delta ADCs with Improved Interferer Robustness. In: Baschirotto, A., Harpe, P., Makinwa, K. (eds) Wideband Continuous-time ΣΔ ADCs, Automotive Electronics, and Power Management. Springer, Cham. https://doi.org/10.1007/978-3-319-41670-0_3
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DOI: https://doi.org/10.1007/978-3-319-41670-0_3
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