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Abstract

The signal bandwidth of delta-sigma analog-to-digital converters has been greatly extended during the last few decades from a few tens of kHz bandwidth for audio to several hundred MHz to date for wireless applications. To enable a wideband and filterless RF radio front-end, high dynamic range and very high linearity of the wideband delta-sigma modulator is required as well. In this chapter the design aspects of high-resolution and wideband continuous-time delta-sigma modulators are presented, from architectural choices to implementation and circuit design examples.

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Notes

  1. 1.

    The noise floor is the average of four measurements.

References

  1. P. Shettigar, S. Pavan, A 15mW 3.6GS/s CT-ΣΔ ADC with 36MHz bandwidth and 83dB DR in 90nm CMOS. ISSCC Digest of Technical Papers, pp. 156–157, Feb 2012

    Google Scholar 

  2. Y. Dong, R. Schreier, W. Yang, S. Korrapati, A. Sheikholeslami, A 235mW CT 0-3 MASH ADC achieving -167dBFS/Hz NSD with 53MHz BW. ISSCC Digest of Technical Papers, pp. 480–481, Feb 2014

    Google Scholar 

  3. M. Bolatkale, L.J. Breems, R. Rutten, K. Makinwa, A 4GHz CT ΣΔ ADC with 70dB DR and -74dBFS THD in 125MHz BW. ISSCC Digest of Technical Papers, pp. 470–471, Feb 2011

    Google Scholar 

  4. H. Shibata, R. Schreier, W. Yang, A. Shaikh, D. Paterson, T. Caldwell, D. Alldred, P.W. Lai, A DC-to-1GHz tunable RF ΣΔ ADC achieving DR=74dB and BW=150MHz at f0=450MHz using 550mW. ISSCC Digest of Technical Papers, pp. 150–151, Feb 2012

    Google Scholar 

  5. D. Yoon, S. Ho, H. Lee, An 85dB-DR 74.6dB-SNDR 50MHz-BW CT MASH ΣΔ Modulator in 28nm CMOS. ISSCC Digest of Technical Papers, pp. 272–273, Feb. 2015

    Google Scholar 

  6. Y. Dong, J. Zhao, W. Yang, T. Caldwell, H. Shibata, R. Schreier, Q. Meng, J. Silva, D. Paterson, J. Gealow, A 930mW 69dB-DR 465MHz-BW CT 1-2 MASH ADC in 28nm CMOS. ISSCC Digest of Technical Papers, pp. 278–279, Feb 2016

    Google Scholar 

  7. L. Breems, M. Bolatkale, H. Brekelmans, S. Bajoria, J. Niehof, R. Rutten, B. Oude-Essink, F.Fritschij, J. Singh, G. Lassche, A 2.2GHz continuous-time ΣΔ ADC with -102dBc THD and 25MHz BW. ISSCC Digest of Technical Papers, pp. 272–273, Feb 2016

    Google Scholar 

  8. Y. Matsuya, K. Uchimura, A. Iwata, T. Kobayashi, M. Ishikawa, T. Yoshitome, A 16-bit oversampling A-to-D conversion technology using triple-integration noise-shaping. IEEE J. Solid-State Circuits, 22(6), 921–929 (1987)

    Google Scholar 

  9. L. Breems, A cascaded continuous-time ΣΔ modulator with 67dB dynamic range in 10MHz bandwidth. ISSCC Digest of Technical Papers, pp. 72–73, Feb 2005

    Google Scholar 

  10. J. Cherry, W. Snelgrove, Clock jitter and quantizer metastability in continuous-time delta-sigma modulators. IEEE Trans. Circuits Syst. II 46, 661–676 (1999)

    Article  Google Scholar 

  11. P. Benabes, M. Keramat, R. Kielbasa, A methodology for designing continuous-time sigma-delta modulators, in Proceedings of European Design and Test Conference, ED TC’97, pp. 46–50, Mar 1997

    Google Scholar 

  12. P. Witte, J. Kauffman, J. Becker, Y. Manoli, M. Ortmanns, A 72 dB-DR CT ΣΔ modulator using digitally estimated auxiliary DAC linearization achieving 88 fJ/conv in a 25 MHz BW. ISSCC Digest of Technical Papers, 2012, pp. 154–156, 2012

    Google Scholar 

  13. J. Kauffman, P. Witte, J. Becker, M. Ortmanns, An 8.5 mW continuous-time ΣΔ modulator with 25 MHz bandwidth using digital background DAC linearization to achieve 63.5 dB SNDR and 81 dB SFDR. IEEE J. Solid State Circuits 46(12), 2869–2881 (2011)

    Article  Google Scholar 

  14. Y.-S. Shu, J.-Y. Tsai, P. Chen, T.-Y. Lo, P.-C.Chiu, A28 fJ/convstep CT delta sigma modulator with 78 dB DR and 18 MHz BW in 28 nm CMOS using a highly digital multibit quantizer. ISSCC Digest of Technical Papers, pp. 268–269, 2013

    Google Scholar 

  15. T. Cataltepe et al., Digitally corrected multi-bit ΣΔ data converters. ISCAS, pp. 647–650, May 1989

    Google Scholar 

  16. M.J. Story, Digital to analogue converter adapted to select input sources based on a preselected algorithm once per cycle of a sampling signal. U.S. Patent 5 138 317, 11 Aug 1992

    Google Scholar 

  17. B.H. Leung, S. Sutarja, Multi-bit sigma-delta A/D converter incorporating a novel class of dynamic element matching techniques. IEEE Trans. Circuits Syst. II 39, 35–51 (1992)

    Article  Google Scholar 

  18. R. Schreier, B. Zhang, Noise-shaped multi-bit D/A converter employing unit elements. Electron. Lett. 31(20), 1712–1713 (1995)

    Article  Google Scholar 

  19. R.T. Baird, T. Fiez, Linearity enhancement of multi-bit ΣΔ A/D and D/A converters using data weighted averaging. IEEE Trans. Circuits Syst. II 42, 753–762 (1995)

    Article  Google Scholar 

  20. T. Kwan, R. Adams, R. Libert, A stereo multi-bit ΣΔ D/A with asynchronous master-clock interface. ISSCC Digest of Technical Papers, vol. 39, Feb 1996, pp. 226–227

    Google Scholar 

  21. I. Galton, Spectral shaping of circuit errors in digital-to-analog converters. IEEE Trans. Circuits Syst. II 44(10), 808–817 (1997)

    Article  Google Scholar 

  22. R.W. Adams, Design and implementation of an audio 18-bit analog-to-digital converter using oversampling techniques. J. Audio Eng. Soc. 34(3), 153–166 (1986)

    Google Scholar 

  23. L. Risbo, R. Hezar, B. Kelleci, H. Kiper, M. Fares, A 108 dB DR, 120 dB THD and 0.5 Vrms output audio DAC with intersymbol interference shaping algorithm in 45 nm. ISSCC Digest of Technical Papers, pp. 484–485, 2011

    Google Scholar 

  24. B. Putter, ΣΔ ADC with finite impulse response feedback DAC. ISSCC Digest of Technical Papers, pp. 76–77, Feb 2004

    Google Scholar 

  25. L. Breems, R. Rutten, R.H.M. van Veldhoven, G. van der Weide, A 56mW continuous-time quadrature cascaded ΣΔ modulator with 77dB DR in a near zero-IF 20MHz band. IEEE J. Solid-State Circuits, pp. 2696–2705, Dec 2012

    Google Scholar 

  26. M. Bolatkale, L. Breems, K. Makinwa, High Speed and Wide Bandwidth Delta-Sigma ADCs (Springer, Dordrecht, 2014)

    Google Scholar 

  27. G. Mitteregger et al., A 20-mW 640-MHz CMOS continuous-time ADC With 20 MHz signal bandwidth, 80-dB dynamic range and 12-bit ENOB. IEEE J. Solid State Circuits 41(12), 2641–2649 (2006)

    Article  Google Scholar 

  28. H. Chae, J. Jeong, G. Manganaro, M. Flynn, A 12mW low-power continuous-time bandpass ΣΔ modulator with 58dB SNDR and 24MHz bandwidth at 200MHz IF. ISSCC Digest of Technical Papers, pp. 148–149, 2012

    Google Scholar 

  29. J. Silva, U. Moon, J. Steensgaard, G. Temes, Wideband low distortion delta-sigma ADC topology. Electron. Lett. 37(12), 737–738 (2001)

    Article  Google Scholar 

  30. E. van der Zwan, E. Dijkmans, A 0.2-mW CMOS Σ∆ modulator for speech coding with 80 dB dynamic range. IEEE J. Solid State Circuits 31(12), 1873–1880 (1996)

    Article  Google Scholar 

  31. S. Zeller et al., A 9th-order continuous time ΣΔ-ADC with X-coupled differential single-opamp resonators MWSCAS, pp. 1–4, Aug 2011

    Google Scholar 

  32. B. Murmann, ADC Performance Survey 1997–2011 [Online]. Available: http://www.stanford.edu/murmann/adcsurvey.html

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Breems, L., Bolatkale, M. (2017). High-Resolution Wideband Continuous-Time ΣΔModulators. In: Baschirotto, A., Harpe, P., Makinwa, K. (eds) Wideband Continuous-time ΣΔ ADCs, Automotive Electronics, and Power Management. Springer, Cham. https://doi.org/10.1007/978-3-319-41670-0_2

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  • DOI: https://doi.org/10.1007/978-3-319-41670-0_2

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