Abstract
This paper presents three different WiFi receiver chain lineups using a high dynamic range continuous time Sigma Delta A/D converter (SD-ADC). The chains tradeoffs are analyzed from the perspective of the ADC design. The key performance indexes are performance, blocker rejection, area and power consumption. Two lineups implement an active filter stage between the mixer and the ADC: one uses a trans-impedance amplifier and the other one a Gm stage. A third lineup avoids the active filtering stage and replaces it with a passive pole. The measurements show that the three lineups achieve the same chain performance and can therefore be directly and fairly compared in the same environment.
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References
R.G.H. Eschauzier, L.P.T. Kerklaan, J.H. Huijsing, A 100 MHz 100 dB operational amplifier with multipath nested Miller compensation structure, in Solid-State Circuits Conference, IEEE Journal of, 1992. Digest of Technical Papers. 39th ISSCC, 1992 IEEE International, 19–21 Feb 1992, pp. 196–197
X. Peng, W. Sansen, AC boosting compensation scheme for low-power multistage amplifiers. IEEE J. Solid State Circuits 39(11), 2074–2079 (2004)
L. Dorrer, F. Kuttner, P. Greco, P. Torta, T. Hartig, A 3-mW 74-dB SNR 2-MHz continuous-time delta-sigma ADC with a tracking ADC quantizer in 0.13-μm CMOS. IEEE J. Solid State Circuits 40(12), 2416–2427 (2005)
J.G. Kauffman, P. Witte, M. Lehmann, J. Becker, Y. Manoli, M. Ortmanns, A 72 dB DR, CT ΣΔ modulator using digitally estimated, auxiliary DAC linearization achieving 88 fJ/conv-step in a 25 MHz BW. IEEE J. Solid State Circuits 49(2), 392–404 (2014)
M. Clara, W. Klatzer, B. Seger, A. Di Giandomenico, L Gori, A 1.5 V 200MS/s 13b 25 mW DAC with randomized nested background calibration in 0.13 μm CMOS, in Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International, 11–15 Feb 2007, pp. 250–600
D.W.J. Groeneveld, H.J. Schouwenaars, H.A.H. Termeer, C.A.A. Bastiaansen, A self-calibration technique for monolithic high-resolution D/A converters. IEEE J. Solid State Circuits 24(6), 1517–1522 (1989)
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Torta, P., Di Giandomenico, A., Dörrer, L., Ceballos, J.L. (2017). WiFi Receiver Evolution in a Dense Blocker Environment. In: Baschirotto, A., Harpe, P., Makinwa, K. (eds) Wideband Continuous-time ΣΔ ADCs, Automotive Electronics, and Power Management. Springer, Cham. https://doi.org/10.1007/978-3-319-41670-0_1
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DOI: https://doi.org/10.1007/978-3-319-41670-0_1
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