Abstract
Architecture of the interconnection network has a great influence on the speed of the multi-core processor design. The main aims of any new architecture are to avoid the latency, and to decrease the cost. In this paper, we proposed new hierarchical interconnection network, in order to build fast parallel computing system. We have evaluated the static network performance of the proposed network such as: node degree, diameter, cost, arc connectivity, bisection width, and wiring complexity. The proposed topology achieved low cost and small diameter comparing to 2D-mesh, and 2D-torus topologies. As well as, it gives good results in the other static parameters. Hence, the proposed network is good solution to improve the performance, and decrease the cost of the interconnection networks for the future generation parallel computing systems.
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Acknowledgments
This research is supported by the project FRGS13-065-0306, Ministry of Education, Government of Malaysia. The authors would like to thank the anonymous reviewers for their constructive comments and suggestions on the paper which have helped to improve the quality of the paper.
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Ali, M.N.M., Rahman, M.M.H., Nor, R.M., Sembok, T.M.B.T. (2016). A High Radix Hierarchical Interconnection Network for Network-on-Chip. In: Meesad, P., Boonkrong, S., Unger, H. (eds) Recent Advances in Information and Communication Technology 2016. Advances in Intelligent Systems and Computing, vol 463. Springer, Cham. https://doi.org/10.1007/978-3-319-40415-8_24
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DOI: https://doi.org/10.1007/978-3-319-40415-8_24
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