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Introduction

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Abstract

Relentless technology scaling has increased the performance and complexity of electronic products by orders of magnitude in the past few decades. A complex system today consists of several chassis, and each of them contains a number of printed circuit boards (PCBs). A typical board consists of many application-specific integrated circuits (ASICs) and memory devices. Each ASIC in turn consists of hundreds of inputs/outputs (I/Os), millions of logic gates, and several tens of millions of bits of embedded memory. Moreover, the operating frequencies of high-speed ASICs are above 1 GHz, and the data rates of high-speed I/Os are up to 6 Gbps Vo et al. (Design for board and system level structural test and diagnosis, 2006, [1]), Tourangeau and Eklow (Test economics - what can a board/system test engineer do to influence supply operation metrics, 2006, [2]). With increasing complexity and higher speeds, defective-parts-per-million (DPPM) rates continue to increase and subtle functional failures are becoming increasingly difficult to detect and diagnose for root-cause identification (Chakraborty et al. A practical approach to comprehensive system test and debug using boundary-scan based test architecture, 2007, [3], Backstrom et al. Remote boundary-scan system test control for the ATCA standard, 2005, [4]).

Keywords

Board-level Data-mining Fault diagnosis Functional failures Machine learning Knowledge-driven 

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Copyright information

© Springer International Publishing Switzerland 2017

Authors and Affiliations

  1. 1.Huawei TechnologiesSanta ClaraUSA
  2. 2.Department of Electrical and Computer EngineeringDuke UniversityDurhamUSA

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