Abstract
In our work, the interface protocol between a processor and memory built using an optical connection is described. We designed a serial interface protocol to simplify a parallel interface between the processor and memory, and implemented the protocol engine to be executed on the interface. There are three main roles of the protocol engines. The first is the data collection and sorting. The second is the data error detection and retransmission request. The third is packetizing the memory command and data.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
Li, L., et al.: Grid memory service architecture for high performance computing. In: Seventh International Conference on Grid and Cooperative Computing, pp. 24–26 (2008)
Okazaki, A., Katayama, Y.: Optical interconnect opportunities for future server memory systems. In: High Performance Computer Architecture, pp. 46–50 (2007)
Batten, C., et al.: Building many-core processor-to-DRAM networks with monolithic CMOS silicon photonics. In: HOTI 2008, pp. 21–30 (2009)
Yin, Y., et al.: Experimental demonstration of optical processor-memory interconnection. In: Advanced Intelligence and Awarenss Internet, pp. 23–25 (2010)
Hadke, A., et al.: Design and evaluation of an optical CPU-DRAM interconnect. In: ICCD, pp. 492–497 (2008)
Brunina, D., et al.: Building data centers with optically connected memory. J. Opt. Soc. Am. 3(8), A40–A48 (2011)
H. M. C. Consortium: Hybrid Memory Cube Specification 1.0 (2013)
Jeddeloh, J., Keeth, B.: Hybrid memory cube new DRAM architecture increases density and performance. In: Symposium on VLSI Technology Digest of Technical Papers, pp. 87–88 (2012)
JEDEC: Wide I/O Single Data Rate (2011)
Kang, U.: 8 Gb 3D DDR3 DRAM using through-silicon-via technology. In: ISSCC 2009, pp. 130–131, 131a (2009)
Lee, W.S.: A Study on the effectiveness of underfill in the high bandwidth memory with TSV. In: IMAPS (2013)
Beamer, S., et al.: Re-architecturing DRAM memory systems with monolothically integrated silicon photonics. In: Proceedings of the 37th Annual International Symposium on Computer Architecture, ISCA 2010, pp. 129–140 (2010)
Udipi, A.N., et al.: Combining memory and a controller with photonics through 3D- stacking to enable scalable and energy-efficient systems. In: ISCA 2011 (2011)
JEDEC: DDR4 SDRAM JESD79-4, September 2012
Jun, H.T., et al.: Disintegrated control for energy-efficient and heterogeneous memory systems. In: HSPA2013, pp. 424–435 (2013)
http://www.bit-tech.net/hardware/cpus/2010/04/21/intel-sandy-bridge-details-of-the-next-gen/1
Brunina, D.: Building data centers with optically connected memory. IEEE/OSA J. Opt. Commun. Networking 3(8), A40–A48 (2011)
Acknowledgement
This work was supported by the ICT R&D program of MSIP/IITP, Korea. [10038764, Silicon Nano Photonics Based Next Generation Computer Interface Platform Technology]
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2016 ICST Institute for Computer Sciences, Social Informatics and Telecommunications Engineering
About this paper
Cite this paper
Kwon, H., Choi, Y. (2016). Protocol for a Simplified Processor-Memory Interface Using High-Speed Serial Link. In: Zhang, Y., Peng, L., Youn, CH. (eds) Cloud Computing. CloudComp 2015. Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering, vol 167. Springer, Cham. https://doi.org/10.1007/978-3-319-38904-2_31
Download citation
DOI: https://doi.org/10.1007/978-3-319-38904-2_31
Published:
Publisher Name: Springer, Cham
Print ISBN: 978-3-319-38903-5
Online ISBN: 978-3-319-38904-2
eBook Packages: Computer ScienceComputer Science (R0)