Optimization-Based Placer

Abstract

This Chapter addresses the optimization-based Placer proposed in the automatic layout generation tool, AIDA-L. Unlike, AIDA-L’s template-based Placer, presented in Chapter 4 of this book, the optimization-based Placer dispenses most of the information contained in the template file. Instead, it applies a multi-objective algorithm to an absolute floorplan representation in order to determine the cells’ locations. Cells can be organized in proximity groups which implement the desired set of symmetry and proximity requirements, bridging the difficulties found on the state-of-the-art works on fulfilling the proximity constraints. Moreover, and to reduce the problem complexity, the intrinsic hierarchy of analog integrated circuit layout is explored, where the Pareto fronts for each proximity group of the problem are combined in a bottom-up fashion. This methodology provides the designer with a Pareto front of placements representing the feasible tradeoffs between the optimization objectives. The first Section of this Chapter covers the general architecture of the Placer, followed by the multi-objective algorithm developed. In Section “XML Description for Optimization-based Placement”, the relevant information contained in the template file is described. After, the problem of placement optimization with constraint handling in absolute coordinates is defined, as well as the hierarchical framework. Finally, the current-flow constraints and current-density considerations taken during placement optimization are detailed, in order to improve circuit’s routability, performance and post-layout reliability.