Abstract
In this paper, we proposed a design methodology for high performance, efficient area, the lower power multiplier for signed-unsigned number. In the first phase, for generating partial products, we proposed the Novel Modified Booth Encoder (NMBE) scheme using 28 transistors, compared to the conventional Modified Booth Encoder (MBE) multiplier of 46 transistors. In the second phase, for reducing several partial products rows into two rows, we have designed the Vertical Column Adder (VCA) with a minimum number of transistors compared to the conventional Partial Product Reduction Tree (PPRT). In the final phase, to obtain the product of multiplication, we have proposed Carry Look-ahead and Carry Select Adder (CLCSA) technique, for high speed addition operation with minimum delay. Hence, the experimental results show that the proposed NMBE multiplier for signed-unsigned number can achieve improvement in speed, area and power dissipation by 38 %, 63 % and 39 % respectively.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
Yeh, W.-C., Jen, C.-W.: High speed booth encoded parallel multiplier design. IEEE Trans. Comput. 49(7), 692–701 (2000)
Kuang, S.-R., Wang, J.-P., Guo, C.-Y.: Modified Booth multipliers with a regular partial product array. IEEE Trans. Circuits Syst.-II 56(5) (2009)
Wang, L.-R., Jou, S.-J., Lee, C.-L.: A well-structured modified booth multiplier design. IEEE (2008). ISBN:978–1-4244-1617-2/08/$25.00 ©2008
Goto, G., Inoue, A., Ohe, R., Kashiwakura, S., Mitarai, S., Tsuru, T., Izawa, T.: A 4.1 ns compact 54 × 54-b multiplier utilising sign-select booth encoders. IEEE J. Solid-State Circuit 32(11) (1997)
Chang, C.-H., Gu, J., Zhang, M.: Ultra low-voltage low-power CMOS 4–2 and 5–2 compressors for fast arithmetic circuits. IEEE Trans. Circuits Syst. 51(10), 1985–1997 (2004)
Huang, Ercegovac: High-performance low-power left-to array multiplier design. IEEE J. Comput. 54(3), 272–283 (2005)
Asadi, Pouya, Navi, Keivan: A novel high-speed 54 × 54 bit multiplier. Am. J. Appl. Sci. 4(9), 666–672 (2007)
Radhakrishnan, D., Preethy, A.P.: Low power CMOS pass logic 4:2 compressor for high speed multiplication. In: Proceedings of 43rd IEEE Midwest Symposium on Circuits and Systems, pp. 1296–1298, 8−11 Aug 2000
Kim, D., Ambler, T.: Low power carry lookahead adder by using dependency between generation and propagation. In: Proceedings of the 2000 Third IEEE International Caracas Conference on Devices, Circuits and Systems. IEEE (2000)
Zlatanovici, R., Kao, S., Nikolic, B.: A 240 ps 64 b carry-lookaheadadder in 90 nm CMOS. IEEE J. Solid-State circuit 44(2), 569–583 (2009)
Nagendra, C., Irwin, M.J., Owens, R.M.: Area-time-power tradeoffs in parallel adders. IEEE Trans. Circuits Syst. II: Analog DSP 43(10), 689–702 (1996)
Kelliher, T.P., Owens, R.M., Irwin, M.J., Hwang, T.-T.: ELM-A fast addition algorithm discovered by a program. IEEE Trans. Comput. 41(9), 1181–1184 (1992)
Shams, A.M., Tarek, K., Bayoumi, M.A.: Performance analysis of low-power 1-bit CMOS full adder cells. IEEE Trans. VLSI Syst. 10(1), 20–28 (2002)
Wang, Y., Pai, C., Song, X.:The design of hybrid carry lookahead/carry select adders. IEEE Trans. Circuits Syst.-II, 49(1), 16–24 (2002)
Lee, S.J., Woo, R., Yoo, H.J.:480 ps 64-bit race logic adder. In: Symposium on VLSI Circuits Digest of Technical Papers, pp. 27–28 (2001)
Kim, J., Joshi, R., Chuang, C.-T., Roy, K.: SOI-optimized 64-bit high-speed CMOS adder design. In: Symposium on VLSI Circuits, pp. 122–125 (2002)
Nève, A., Schettler, H., Ludwig, T., Flandre, D.: Power-delay product minimization in high-performance 64-bit carry select adders. IEEE Trans. VLSI. Syst. 12(3), 235–244 (2004)
Prasad, K., Parhi, K.K.: Low-power 4-2 and 5-2 compressors. In: Proceedings of the 35th Asilomar Conference on Signals, Systems and Computers, vol. 1, pp. 129–133 (2001)
Kwon, O., Nowka, K., Swartzlander, E.E.: A 16-bit _ 16-bit MAC design using fast 5:2 compressor. In: Proceedings of IEEE International Conference on Application Specific System, Architectures, Processors, pp. 235–243 (2000)
Oklobdzija, V., Vileger, D., Liu,S.S.: A method for speed optimized partial product reduction and generation of fast parallel multipliers using an algorithmic approach. IEEE Trans. Comput. 45(3), 294–306 (1996)
Wallace, C.S.: A suggestion for a fast multiplier. IEEE Trans. Electron. Comput. 14–17 (1964)
Hwang, K.: Computer Arithmetic: Principles, Architecture, and Design, chapter 3, p. 81. Wiley (1976)
Weste, N.H.E., David Harris, D., Banerjee, A.: CMOS VLSI Design: A circuits and Systems Perspective, pp. 347–349. Pearson Education (2006)
Pucknell D.A., Eshraghan, K.: Basic VLSI Design, pp. 242–243, 3rd edn. PHI Publication (2003)
Hwang, K., Briggs, F.A.: Compter Architecture and Parallel Processing, pp. 170–176. McGraw Hill International edition (1985)
Wolf, W.: Modern VLSI Design System-on-chip Design, chapter 6, 3rd edn. Pearson Education Asia (2002)
Cheng, K.H., et al.: The improvement of conditional sum adder for low power applications. In: Proceedings of 11th Annual IEEE International ASIC Conference, pp. 131–134 (1998)
Acknowledgments
The authors would like to acknowledge the Cheif Executive Professor T N Nagbhushan, and all the members of the JSS Research foundation, SJCE Campus, Mysore, for all the facilities provided for this research work.
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2016 Springer International Publishing Switzerland
About this paper
Cite this paper
Rajput, R.P., Shanmukha Swamy, M.N. (2016). High Speed, Efficient Area, Low Power Novel Modified Booth Encoder Multiplier for Signed-Unsigned Number. In: Silhavy, R., Senkerik, R., Oplatkova, Z., Silhavy, P., Prokopova, Z. (eds) Artificial Intelligence Perspectives in Intelligent Systems. Advances in Intelligent Systems and Computing, vol 464. Springer, Cham. https://doi.org/10.1007/978-3-319-33625-1_29
Download citation
DOI: https://doi.org/10.1007/978-3-319-33625-1_29
Published:
Publisher Name: Springer, Cham
Print ISBN: 978-3-319-33623-7
Online ISBN: 978-3-319-33625-1
eBook Packages: EngineeringEngineering (R0)