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High Speed, Efficient Area, Low Power Novel Modified Booth Encoder Multiplier for Signed-Unsigned Number

  • Ravindra P RajputEmail author
  • M N Shanmukha Swamy
Conference paper
Part of the Advances in Intelligent Systems and Computing book series (AISC, volume 464)

Abstract

In this paper, we proposed a design methodology for high performance, efficient area, the lower power multiplier for signed-unsigned number. In the first phase, for generating partial products, we proposed the Novel Modified Booth Encoder (NMBE) scheme using 28 transistors, compared to the conventional Modified Booth Encoder (MBE) multiplier of 46 transistors. In the second phase, for reducing several partial products rows into two rows, we have designed the Vertical Column Adder (VCA) with a minimum number of transistors compared to the conventional Partial Product Reduction Tree (PPRT). In the final phase, to obtain the product of multiplication, we have proposed Carry Look-ahead and Carry Select Adder (CLCSA) technique, for high speed addition operation with minimum delay. Hence, the experimental results show that the proposed NMBE multiplier for signed-unsigned number can achieve improvement in speed, area and power dissipation by 38 %, 63 % and 39 % respectively.

Keywords

MBE NMBE PPG PPRT CLA CLCSA VCA 

Notes

Acknowledgments

The authors would like to acknowledge the Cheif Executive Professor T N Nagbhushan, and all the members of the JSS Research foundation, SJCE Campus, Mysore, for all the facilities provided for this research work.

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Copyright information

© Springer International Publishing Switzerland 2016

Authors and Affiliations

  1. 1.JSS Research Foundation, SJCE CampusMysore UniversityMysoreIndia

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