High Speed, Efficient Area, Low Power Novel Modified Booth Encoder Multiplier for Signed-Unsigned Number

  • Ravindra P RajputEmail author
  • M N Shanmukha Swamy
Conference paper
Part of the Advances in Intelligent Systems and Computing book series (AISC, volume 464)


In this paper, we proposed a design methodology for high performance, efficient area, the lower power multiplier for signed-unsigned number. In the first phase, for generating partial products, we proposed the Novel Modified Booth Encoder (NMBE) scheme using 28 transistors, compared to the conventional Modified Booth Encoder (MBE) multiplier of 46 transistors. In the second phase, for reducing several partial products rows into two rows, we have designed the Vertical Column Adder (VCA) with a minimum number of transistors compared to the conventional Partial Product Reduction Tree (PPRT). In the final phase, to obtain the product of multiplication, we have proposed Carry Look-ahead and Carry Select Adder (CLCSA) technique, for high speed addition operation with minimum delay. Hence, the experimental results show that the proposed NMBE multiplier for signed-unsigned number can achieve improvement in speed, area and power dissipation by 38 %, 63 % and 39 % respectively.





The authors would like to acknowledge the Cheif Executive Professor T N Nagbhushan, and all the members of the JSS Research foundation, SJCE Campus, Mysore, for all the facilities provided for this research work.


  1. 1.
    Yeh, W.-C., Jen, C.-W.: High speed booth encoded parallel multiplier design. IEEE Trans. Comput. 49(7), 692–701 (2000)Google Scholar
  2. 2.
    Kuang, S.-R., Wang, J.-P., Guo, C.-Y.: Modified Booth multipliers with a regular partial product array. IEEE Trans. Circuits Syst.-II 56(5) (2009)Google Scholar
  3. 3.
    Wang, L.-R., Jou, S.-J., Lee, C.-L.: A well-structured modified booth multiplier design. IEEE (2008). ISBN:978–1-4244-1617-2/08/$25.00 ©2008Google Scholar
  4. 4.
    Goto, G., Inoue, A., Ohe, R., Kashiwakura, S., Mitarai, S., Tsuru, T., Izawa, T.: A 4.1 ns compact 54 × 54-b multiplier utilising sign-select booth encoders. IEEE J. Solid-State Circuit 32(11) (1997)Google Scholar
  5. 5.
    Chang, C.-H., Gu, J., Zhang, M.: Ultra low-voltage low-power CMOS 4–2 and 5–2 compressors for fast arithmetic circuits. IEEE Trans. Circuits Syst. 51(10), 1985–1997 (2004)CrossRefGoogle Scholar
  6. 6.
    Huang, Ercegovac: High-performance low-power left-to array multiplier design. IEEE J. Comput. 54(3), 272–283 (2005)CrossRefGoogle Scholar
  7. 7.
    Asadi, Pouya, Navi, Keivan: A novel high-speed 54 × 54 bit multiplier. Am. J. Appl. Sci. 4(9), 666–672 (2007)CrossRefGoogle Scholar
  8. 8.
    Radhakrishnan, D., Preethy, A.P.: Low power CMOS pass logic 4:2 compressor for high speed multiplication. In: Proceedings of 43rd IEEE Midwest Symposium on Circuits and Systems, pp. 1296–1298, 8−11 Aug 2000Google Scholar
  9. 9.
    Kim, D., Ambler, T.: Low power carry lookahead adder by using dependency between generation and propagation. In: Proceedings of the 2000 Third IEEE International Caracas Conference on Devices, Circuits and Systems. IEEE (2000)Google Scholar
  10. 10.
    Zlatanovici, R., Kao, S., Nikolic, B.: A 240 ps 64 b carry-lookaheadadder in 90 nm CMOS. IEEE J. Solid-State circuit 44(2), 569–583 (2009)Google Scholar
  11. 11.
    Nagendra, C., Irwin, M.J., Owens, R.M.: Area-time-power tradeoffs in parallel adders. IEEE Trans. Circuits Syst. II: Analog DSP 43(10), 689–702 (1996)Google Scholar
  12. 12.
    Kelliher, T.P., Owens, R.M., Irwin, M.J., Hwang, T.-T.: ELM-A fast addition algorithm discovered by a program. IEEE Trans. Comput. 41(9), 1181–1184 (1992)CrossRefGoogle Scholar
  13. 13.
    Shams, A.M., Tarek, K., Bayoumi, M.A.: Performance analysis of low-power 1-bit CMOS full adder cells. IEEE Trans. VLSI Syst. 10(1), 20–28 (2002)Google Scholar
  14. 14.
    Wang, Y., Pai, C., Song, X.:The design of hybrid carry lookahead/carry select adders. IEEE Trans. Circuits Syst.-II, 49(1), 16–24 (2002)Google Scholar
  15. 15.
    Lee, S.J., Woo, R., Yoo, H.J.:480 ps 64-bit race logic adder. In: Symposium on VLSI Circuits Digest of Technical Papers, pp. 27–28 (2001)Google Scholar
  16. 16.
    Kim, J., Joshi, R., Chuang, C.-T., Roy, K.: SOI-optimized 64-bit high-speed CMOS adder design. In: Symposium on VLSI Circuits, pp. 122–125 (2002)Google Scholar
  17. 17.
    Nève, A., Schettler, H., Ludwig, T., Flandre, D.: Power-delay product minimization in high-performance 64-bit carry select adders. IEEE Trans. VLSI. Syst. 12(3), 235–244 (2004)Google Scholar
  18. 18.
    Prasad, K., Parhi, K.K.: Low-power 4-2 and 5-2 compressors. In: Proceedings of the 35th Asilomar Conference on Signals, Systems and Computers, vol. 1, pp. 129–133 (2001)Google Scholar
  19. 19.
    Kwon, O., Nowka, K., Swartzlander, E.E.: A 16-bit _ 16-bit MAC design using fast 5:2 compressor. In: Proceedings of IEEE International Conference on Application Specific System, Architectures, Processors, pp. 235–243 (2000)Google Scholar
  20. 20.
    Oklobdzija, V., Vileger, D., Liu,S.S.: A method for speed optimized partial product reduction and generation of fast parallel multipliers using an algorithmic approach. IEEE Trans. Comput. 45(3), 294–306 (1996)Google Scholar
  21. 21.
    Wallace, C.S.: A suggestion for a fast multiplier. IEEE Trans. Electron. Comput. 14–17 (1964)Google Scholar
  22. 22.
    Hwang, K.: Computer Arithmetic: Principles, Architecture, and Design, chapter 3, p. 81. Wiley (1976)Google Scholar
  23. 23.
    Weste, N.H.E., David Harris, D., Banerjee, A.: CMOS VLSI Design: A circuits and Systems Perspective, pp. 347–349. Pearson Education (2006)Google Scholar
  24. 24.
    Pucknell D.A., Eshraghan, K.: Basic VLSI Design, pp. 242–243, 3rd edn. PHI Publication (2003)Google Scholar
  25. 25.
    Hwang, K., Briggs, F.A.: Compter Architecture and Parallel Processing, pp. 170–176. McGraw Hill International edition (1985)Google Scholar
  26. 26.
    Wolf, W.: Modern VLSI Design System-on-chip Design, chapter 6, 3rd edn. Pearson Education Asia (2002)Google Scholar
  27. 27.
    Cheng, K.H., et al.: The improvement of conditional sum adder for low power applications. In: Proceedings of 11th Annual IEEE International ASIC Conference, pp. 131–134 (1998)Google Scholar

Copyright information

© Springer International Publishing Switzerland 2016

Authors and Affiliations

  1. 1.JSS Research Foundation, SJCE CampusMysore UniversityMysoreIndia

Personalised recommendations