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Placement of VLSI Fragments Based on a Multilayered Approach

  • Vladimir KureichikJr.Email author
  • Vladimir Kureichik
  • Viktoria Bova
Conference paper
Part of the Advances in Intelligent Systems and Computing book series (AISC, volume 464)

Abstract

The article is connected with solving one of the main problems of automated engineering design stage of electronic computing equipment of placement of VLSI fragments in a limited area of a construction. Placement of VLSI fragments is NP-hard. The paper tells about the multilayered approach to solving this problem. Description of the placement problem is given in this work. Definition of the problem of placement of VLSI fragments in a grate is formulated. New search architecture based on the multilayered approach is proposed. The main difference of the suggested approach is division of the search process into two stages. At each stage different methods are used. This approach gives an opportunity to vectorize the solving process and to make optimal and quasioptimal solutions in a time similar to iteration algorithm realization time. A simulation experiment was conducted through the example of test cases (benchmarks). Quality of placement based on the suggested approach is averagely 2 % higher than quality of known algorithms such as Capo 8.6, Feng Shui 2.0, Dragon 2.23 what indicates the effectiveness of the combined search. A number of conducted test and experiments showed the prospects of using this approach. The time complexity of the suggested algorithms is ≈O(nlogn) at the best case and –O(n3) at the worst one.

Keywords

Combined search Design VLSI Genetic algorithm 

Notes

Acknowledgment

This research is supported by the Ministry of Education and Science of the Russian Federation, the project # 8.823.2014.

References

  1. 1.
    Alpert, C., Mehta, D., Sapatnekar, S.: Handbook of Algorithms for Physical Design Automation, p. 1024. Auerbach Publications, New York, USA (2009)Google Scholar
  2. 2.
    Bunglowala, A., Singhi, B.M., Verma, A., IEEE: Optimization of hybrid and local search algorithms for standard cell placement in VLSI design. In: 2009 International Conference on Advances in Recent Technologies in Communication and Computing (ARTCom 2009), pp. 826–828 (2009)Google Scholar
  3. 3.
    Chen, G., Guo, W., Cheng, H., Fen, X., Fang, X.: VLSI Floorplanning Based on Particle Swarm Optimization (2008)Google Scholar
  4. 4.
    Fidanova, S., Pop, P.: An improved hybrid ant-local search algorithm for the partition graph coloring problem. J. Comput. Appl. Math. 293, 55–61 (2016)MathSciNetCrossRefzbMATHGoogle Scholar
  5. 5.
    Markov, I.L., Hu, J., Kim, M.-C.: Progress and challenges in VLSI placement research. Proc. IEEE 103, 1985–2003 (2015)CrossRefGoogle Scholar
  6. 6.
    Swetha, R.R., Devi, S.K.A., Yousef, S.: Hybrid partitioning algorithm for area minimization in circuits. In: International Conference on Computer, Communication and Convergence (ICCC 2015), vol. 48, pp. 692–698 (2015)Google Scholar
  7. 7.
    Zhao, H., Destech Publicat, I.: VLSI placement design using genetic algorithms. In: 2014 International Conference on Mechanical Engineering and Automation (ICMEA), pp. 436–439 (2014)Google Scholar
  8. 8.
    Kureichik, V.V., Zaruba, D.V.: Partitioning of ECE schemes components based on modified graph coloring algorithm. In: 12th IEEE East-West Design and Test Symposium, EWDTS 2014 (2014)Google Scholar
  9. 9.
    Kureichik, V.V., Zaruba, D.V.: The bioinspired algorithm of electronic computing equipment schemes elements placement. In: Silhavy, R., Senkerik, R., Oplatkova, Z.K., Prokopova, Z., Silhavy, P. (eds.) 4th Computer Science On-line Conference, CSOC 2015, vol. 347, pp. 51–58. Springer (2015)Google Scholar
  10. 10.
    Yurevich Zaporozhets, D., Victorovna Zaruba, D., Kureichik, V.V.: Hybrid bionic algorithms for solving problems of parametric optimization. World Appl. Sci. J. 23, 1032–1036 (2013)Google Scholar
  11. 11.
    Zaporozhets, D.U., Zaruba, D.V., Kureichik, V.V.: Representation of solutions in genetic VLSI placement algorithms. In: 12th IEEE East-West Design and Test Symposium, EWDTS 2014 (2014)Google Scholar
  12. 12.
    Zaporozhets, D., Zaruba, D.V., Kureichik, V.V.: Hierarchical approach for VLSI components placement. In: Silhavy, R., Senkerik, R., Oplatkova, Z.K., Prokopova, Z., Silhavy, P. (eds.) 4th Computer Science On-line Conference, CSOC 2015, vol. 347, pp. 79–87. Springer (2015)Google Scholar

Copyright information

© Springer International Publishing Switzerland 2016

Authors and Affiliations

  • Vladimir KureichikJr.
    • 1
    Email author
  • Vladimir Kureichik
    • 1
  • Viktoria Bova
    • 1
  1. 1.Southern Federal UniversityRostov-on-DonRussia

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