Abstract
In this chapter, we look back at what we have done in this book. Section 9.1 briefly discussed the motivation behind the work, and lists the main contributions from Chaps. 2–7. Additionally, we provide a slightly broader perspective on the presented content and its relation to the research field in which we operate. This leads to suggestions for future research directions in Sect. 9.2.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
Akesson B, Goossens K (2011) Memory controllers for real-time embedded systems. Embedded systems series. Springer, New York
Goossens K, Azevedo A, Chandrasekar K, Gomony MD, Goossens S, Koedam M, Li Y, Mirzoyan D, Molnos A, Nejad AB, Nelson A, Sinha S (2013) Virtual execution platforms for mixed-time-criticality systems: the CompSOC architecture and design flow. SIGBED Rev 10(3):23–34
Goossens S, Akesson B, Koedam M, Nejad AB, Nelson A, Goossens K (2013) The CompSOC design flow for virtual execution platforms. In: Proceedings of the 10th FPGAworld conference, pp 7:1–7:6
Chandrasekar K (2014) High-level power estimation and optimization of DRAMs. Ph.D. thesis, Delft University of Technology
Chandrasekar K, Goossens S, Weis C, Koedam M, Akesson B, Wehn N, Goossens K (2014) Exploiting expendable process-margins in DRAMs for run-time performance optimization. In: Design, automation and test in Europe conference and exhibition (DATE), pp 1–6
Weis C, Jung M, Ehses P, Santos C, Vivet P, Goossens S, Koedam M, Wehn N (2015) Retention time measurements and modelling of bit error rates of wide I/O DRAM in MPSOCs. In: Design, automation and test in Europe conference and exhibition (DATE), pp 495–500
Micron (2007) Calculating memory system power for DDR3. Technical report, Micron Technology Inc. TN-41-01
Jalle J, Quinones E, Abella J, Fossati L, Zulianello M, Cazorla F (2014) A dual-criticality memory controller (DCmc): Proposal and evaluation of a space case study. In: Real-time systems symposium, pp 207–217
Krishnapillai Y, Pei Wu Z, Pellizzoni R (2014) ROC: a rank-switching, open-row DRAM controller for time-predictable systems. In: Euromicro conference on real-time systems (ECRTS), pp 27–38
Kim H, Broman D, Lee EA, Zimmer M, Shrivastava A, Oh J (2015) A predictable and command-level priority-based DRAM controller for mixed-criticality systems. In: Real-time and embedded technology and application symposium (RTAS)
Fang K, Zheng H, Lin J, Zhang Z, Zhu Z (2014) Mini-rank: a power-efficient DDRx DRAM memory architecture. IEEE Trans Comput 63(6):1500–1512
Reineke J, Liu I, Patel HD, Kim S, Lee EA (2011) PRET DRAM controller: bank privatization for predictability and temporal isolation. In: Proceedings of CODES+ISSS, pp 99–108
Ecco L, Tobuschat S, Saidi S, Ernst R (2014) A mixed critical memory controller using bank privatization and fixed priority scheduling. In: Embedded and real-time computing systems and applications (RTCSA)
Nelson A, Goossens K, Akesson B (2015) Dataflow formalisation of real-time streaming applications on a composable and predictable multi-processor SOC. J Syst Archit
Author information
Authors and Affiliations
Corresponding author
Rights and permissions
Copyright information
© 2016 Springer International Publishing Switzerland
About this chapter
Cite this chapter
Goossens, S., Chandrasekar, K., Akesson, B., Goossens, K. (2016). Conclusions and Future Work. In: Memory Controllers for Mixed-Time-Criticality Systems. Embedded Systems. Springer, Cham. https://doi.org/10.1007/978-3-319-32094-6_9
Download citation
DOI: https://doi.org/10.1007/978-3-319-32094-6_9
Published:
Publisher Name: Springer, Cham
Print ISBN: 978-3-319-32093-9
Online ISBN: 978-3-319-32094-6
eBook Packages: EngineeringEngineering (R0)