Abstract
Systems generally operate in dynamic environments where the mix of active applications or use-case is not constant during the execution. This chapter shows how the configuration of our memory controller is adaptable to these changes, starting with an overview of the reconfiguration options offered by our architecture in Sect. 7.1. Section 7.2 describes how predictable and composable performance guarantees are defined for clients that remain active during reconfiguration, and Sect. 7.3 discusses the implication this has on the reconfiguration options we can safely use for these clients. Reconfiguring an arbiter while retaining predictable performance guarantees is not trivial: Sect. 7.4 shows how to construct and use a TDM arbiter that has this property. Section 7.5 evaluates the contributions in this chapter through experiments with our SystemC model and the VHDL instance of our controller.
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We recognize that it may be beneficial to apply such permutations for certain applications with regular but nonlinear addressing strides, but in general the data that a client reads should match the data that it wrote earlier.
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Goossens, S., Chandrasekar, K., Akesson, B., Goossens, K. (2016). Reconfiguration. In: Memory Controllers for Mixed-Time-Criticality Systems. Embedded Systems. Springer, Cham. https://doi.org/10.1007/978-3-319-32094-6_7
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DOI: https://doi.org/10.1007/978-3-319-32094-6_7
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