Abstract
As technology scales, multiple bit upsets (MBUs) have shown prominent effect, thus affecting the reliability of memory to a great extent. In order to mitigate MBUs errors, interleaving schemes together with single error correction (SEC) codes can be used to provide the greatest protection for advanced computer memories. In this paper, an algorithm of iterative scrubbing strategy (ISS) is proposed for the optimal interleaving distance (ID), which should be maximized under some conditions. The proposed algorithm should keep the complexity and the area overhead of designing ID as low as possible without compromising memory reliability. The key principle is to take advantage of the locality of MBU errors and to realize efficient scrubbing. The efficiency of the proposed approach will be compared with conventional strategy.
Keywords
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
Georgakos, G., Huber, P., Ostermayr, M., Amirante, E., Ruckerbauer, F.: Investigation of increased multi-bit failure rate due to neutron induced seu in advanced embedded srams. In: 2007 IEEE Symposium on VLSI Circuits, pp. 80–81. IEEE (2007)
Seifert, N., Gill, B., Foley, K., Relangi, P.: Multi-cell upset probabilities of 45nm high-k+ metal gate sram devices in terrestrial and space environments. In: IEEE International Reliability Physics Symposium, IRPS 2008, pp. 181–186. IEEE (2008)
Chen, C.-L., Hsiao, M.: Error-correcting codes for semiconductor memory applications: a state-of-the-art review. IBM J. Res. Dev. 28(2), 124–134 (1984)
Cher, C.-Y., Muller, K.P., Haring, R.A., Satterfield, D.L., Musta, T.E., Gooding, T., Davis, K.D., Dombrowa, M.B., Kopcsay, G.V., Senger, R.M., et al.: Soft error resiliency characterization on ibm bluegene/q processor. In: ASP-DAC, pp. 385–387 (2014)
Park, A., Narayanan, V., Bowman, K., Atallah, F., Artieri, A., Yoon, S.S., Yuen, K., Hansquine, D.: Exploiting error-correcting codes for cache minimum supply voltage reduction while maintaining coverage for radiation-induced soft errors. In: 2014 IEEE Proceedings of the Custom Integrated Circuits Conference (CICC), pp. 1–4. IEEE (2014)
Lee, S., Baeg, S., Reviriego, P.: Memory reliability model for accumulated and clustered soft errors. IEEE Trans. Nucl. Sci. 58(5), 2483–2492 (2011)
Reviriego, P., Maestro, J.A., Cervantes, C.: Reliability analysis of memories suffering multiple bit upsets. IEEE Trans. Device Mater. Reliab. 7(4), 592–601 (2007)
Maniatakos, M., Michael, M.K., Makris, Y.: Vulnerability-based interleaving for multi-bit upset (mbu) protection in modern microprocessors. In: 2012 IEEE International Test Conference (ITC), pp. 1–8. IEEE (2012)
Baeg, S., Wen, S., Wong, R.: Minimizing soft errors in tcam devices: a probabilistic approach to determining scrubbing intervals. IEEE Trans. Circ. Syst. I Regul. Pap. 57(4), 814–822 (2010)
Reviriego, P., Maestro, J.A., Baeg, S., Wen, S., Wong, R.: Protection of memories suffering mcus through the selection of the optimal interleaving distance. IEEE Trans. Nucl. Sci. 57(4), 2124–2128 (2010)
Palframan, D.J., Kim, N.S., Lipasti, M.H.: Precision-aware soft error protection for GPUs. In: 20th International Symposium on High Performance Computer Architecture (HPCA), Proceedings, pp. 49–59. IEEE (2014)
Mukherjee, S.S., Emer, J., Fossum, T., Reinhardt, S.K.: Cache scrubbing in microprocessors: myth or necessity? In: 10th IEEE Pacific Rim International Symposium on Dependable Computing, Proceedings, pp. 37–42. IEEE (2004)
Baeg, S., Wen, S., Wong, R.: Sram interleaving distance selection with a soft error failure model. IEEE Trans. Nucl. Sci. 56(4), 2111–2118 (2009)
Maestro, J.A., Reviriego, P., Baeg, S., Wen, S., Wong, R.: Mitigating the effects of large multiple cell upsets (mcus) in memories. ACM Trans. Des. Autom. Electron. Syst. (TODAES) 16(4), 45 (2011)
Dutta, A., Touba, N.A.: Multiple bit upset tolerant memory using a selective cycle avoidance based sec-ded-daec code. In: 25th IEEE VLSI Test Symposium, pp. 349–354. IEEE (2007)
Reviriego, P., Maestro, J.A., Baeg, S.: Optimizing scrubbing sequences for advanced computer memories. IEEE Trans. Device Mater. Reliab. (T-DMR) 10(2), 192–200 (2010)
Tipton, A.D., Pellish, J.A., Hutson, J.M., Baumann, R., Deng, X., Marshall, A., Xapsos, M.A., Kim, H.S., Friendlich, M.R., Campola, M.J., et al.: Device-orientation effects on multiple-bit upset in 65 nm srams. IEEE Trans. Nucl. Sci. 55(6), 2880–2885 (2008)
Ibe, E., Taniguchi, H., Yahagi, Y., Shimbo, K.-I., Toba, T.: Impact of scaling on neutron-induced soft error in srams from a 250 nm to a 22 nm design rule. IEEE Trans. Electron Devices 57(7), 1527–1538 (2010)
Saleh, A.M., Serrano, J.J., Patel, J.H.: Reliability of scrubbing recovery-techniques for memory systems. IEEE Trans. Reliab. 39(1), 114–122 (1990)
Acknowledgment
This research work was partially supported by 863 Hi-Tech Program in China under grant No.2011AA040502, and the 973 Program in China under grant 2009CB320705. We thank all of the anonymous reviewers of this work for their valuable comments.
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2016 Springer International Publishing Switzerland
About this paper
Cite this paper
Wang, H., Wang, Y. (2016). ISS: An Iterative Scrubbing Strategy for Improving Memory Reliability Against MBU. In: Zu, Q., Hu, B. (eds) Human Centered Computing. HCC 2016. Lecture Notes in Computer Science(), vol 9567. Springer, Cham. https://doi.org/10.1007/978-3-319-31854-7_38
Download citation
DOI: https://doi.org/10.1007/978-3-319-31854-7_38
Published:
Publisher Name: Springer, Cham
Print ISBN: 978-3-319-31853-0
Online ISBN: 978-3-319-31854-7
eBook Packages: Computer ScienceComputer Science (R0)