Abstract
The success of the electronics industry has been due in large part to advances in silicon integrated circuit (IC) technology based on planar processing, which involves the fabrication of fine structures on semiconductor wafers via a sequence of steps, layer-by-layer. What began as silicon microfabrication has now developed into nanofabrication: As shown in Fig. 2.1, feature sizes of silicon ICs reached the nanoscale over a decade ago, propelled by Moore’s Law or the continued exponential increase in the number of transistors per IC over the past 50 years. Virtually all the electronics technology in use today (digital and/or analog) is built upon silicon ICs created using planar processing methods, as described in this chapter.
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Notes
- 1.
For the genesis of Moore’s Law see G.E. Moore, Electronics 38, 114 (1965).
- 2.
At present silicon electronics can contain upwards of 1 billion transistors per IC or chip.
- 3.
Steps 2–7 are essentially applied in a parallel manner across the surface of a wafer, which leads to a roughly constant manufacturing cost per unit area regardless of the number of components created—from individual discrete devices to chips containing billions of devices.
- 4.
Multiple planarization polishing steps are also included at various points during processing.
- 5.
The term “lithography” originates from the traditional stone printing surfaces used for writing/transferring patterns and thus lithos the Greek word for stone.
- 6.
Also known simply as resist.
- 7.
See, e.g., G.M. Wallraff, W.D. Hinsberg, Chem. Rev. 99, 1801 (1999).
- 8.
Lord Rayleigh, Phil. Mag. S. 5 8, 261 (1879).
- 9.
The numerical aperture is defined as \(n\sin \theta\), where n is the incident refractive index and \(\theta\) is the angular aperture of the lens or the half-angle of the maximum light cone that can be collected.
- 10.
Dopants are usually added from the vapor phase using either a thermal diffusion process, or electric field-assisted ion-implantation for more accurate placement near the semiconductor surface.
- 11.
Most types of thin film deposition from the vapor phase occur inside an enclosed chamber that is either under vacuum or filled with appropriate gas species.
- 12.
See Chap. 3 for details on electron beams; formation and focusing.
- 13.
This will depend on the particular fabrication technology “node”—at present 14 nm, with 10 nm next on the horizon.
References
D.P. Sanders, Chem. Rev. 110, 321 (2010)
J.D. Plummer, M.D. Deal, P.B. Griffin, Silicon VLSI Technology (Prentice Hall, New Jersey, 2000)
S.A. Campbell, The Science and Engineering of Microelectronic Fabrication, 2nd edn. (Oxford University Press, New York, 2001)
International Technology Roadmap for Semiconductors, 2013–2015; www.itrs2.net
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Papadopoulos, C. (2016). Silicon Planar Processing and Photolithography. In: Nanofabrication. SpringerBriefs in Materials. Springer, Cham. https://doi.org/10.1007/978-3-319-31742-7_2
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DOI: https://doi.org/10.1007/978-3-319-31742-7_2
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