Abstract
A common use for Field-Programmable Gate Arrays (FPGAs) is the implementation of hardware accelerators. A way of doing so is to specify the internal logic of such accelerators by using Hardware Description Languages (HDLs). However, HDLs rely on the expertise of developers and their knowledge about hardware development with FPGAs. Regarding this, efforts have been focused on developing High-Level Synthesis (HLS) tools in an attempt to increase the overall abstraction level required for using FPGAs. However, the solutions presented by such tools are commonly considered inefficient in comparison to the ones achieved by a specialized hardware designer. An alternative solution to program FPGAs is the use of Domain-Specific Languages (DSLs), as they can provide higher abstraction levels than HDLs still allowing the developers to deal with specific issues leading to more efficient designs and not always covered by HLS tools. In this chapter we present our recent work on a DSL named LALP (Language for Aggressive Loop Pipelining), which has been designed focusing on the development of FPGA-based, aggressively pipelined, hardware accelerators. We present the recent LALP extensions and the challenges we are facing regarding to the compilation of LALP to FPGAs.
Keywords
- FPGA-based Accelerators
- For Field Programmable Gate Array (FPGA)
- Hardware Description Language (HDLs)
- Loop Pipelining
- Single BRAM
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Notes
- 1.
Freely available in http://www.eda.org/fphdl/.
- 2.
References
Menotti, R., Cardoso, J.M.P., Fernandes, M.M., Marques, E: LALP: a language to program custom FPGA-based acceleration engines. Int. J. Parallel Prog. 40 (3), 262–289 (2012)
Cardoso, J.M.P., Neto, H.C.: Macro-based hardware compilation of JavaTM bytecodes into a dynamic reconfigurable computing system. In: Proceedings of the 7th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, pp. 2–11. IEEE (1999)
IEEE: IEEE Standard for Binary Floating-Point Arithmetic, ANSI/IEEE Std 754-1985 (1985)
Feist, T.: Vivado Design Suite. White Paper, Xilinx Inc. (2012)
Andrew, C., et al.: LegUp: an open-source high-level synthesis tool for FPGA-based processor/accelerator systems. ACM Trans. Embed. Comput. Syst. 13 (2), 24:1–24:27 (2013)
Villarreal, J., Park, A., Najjar, W., Halstead, R.: Designing modular hardware accelerators in c with roccc 2.0. In: 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, pp. 127–134. IEEE (2010)
Huong, G.N.T., Kim, S.W.: Gcc2verilog compiler toolset for complete translation of c programming language into verilog hdl. ETRI J. 33 (5), 731–740 (2011)
Rotem, N.: Online: http://www.c-to-verilog.com/ (2010)
de Oliveira, C.B., Cardoso, J.M.P., Marques, E.: High-level synthesis from C vs. a DSL-based approach. In: IEEE International Parallel Distributed Processing Symposium Workshops (IPDPSW), pp. 257–262 (2014)
Mencer, O., Hubert, H., Morf, M., Flynn, M.: StReAm: object-oriented programming of stream architectures using PAM-Blox. In: IEEE Symposium on Field-Programmable Custom Computing Machines, pp. 309–310 (2000)
Mencer, O., Platzner, M., Morf, M., Flynn, M.: Object-oriented domain specific compilers for programming FPGAs. IEEE Trans. Very Large Scale Integr. VLSI Syst. 9 (1), 205–210 (2001)
Mencer, O., Morf, M., Flynn, M.: PAM-Blox: high performance FPGA design for adaptive computing. In: IEEE Symposium on FPGAs for Custom Computing Machines, pp. 167–174 (1998)
Mencer, O.: ASC: a stream compiler for computing with FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25 (9), 1603–1617 (2006)
Haglund, P., Mencer, O., Luk, W., Tai, B.: Hardware design with a scripting language. In: Peter, Y.K.C., Constantinides, G.A. (eds.) Field Programmable Logic and Application. Lecture Notes in Computer Science, vol. 2778, pp. 1040–1043. Springer, Berlin/Heidelberg (2003)
Fu, H., Gan, L., Clapp, R.G., Ruan, H., Pell, O., Mencer, O., Flynn, M., Huang, X., Yang, G.: Scaling reverse time migration performance through reconfigurable dataflow engines. IEEE Micro 34 (1), 30–40 (2014)
Pell, O., Bower, J., Dimond, R., Mencer, O., Flynn, M.J.: Finite-difference wave propagation modeling on special-purpose dataflow machines. IEEE Trans. Parallel Distrib. Syst. 24 (5), 906–915 (2013)
The OpenSPL Consortium: OpenSPL: Revealing the Power of Spatial Computing. White Paper, The OpenSPL Consortium (2013)
Papakonstantinou, A., Gururaj, K., Stratton, J.A., Chen, D., Cong, J., Hwu, W.-M.W.: Efficient compilation of cuda kernels for high-performance computing on FPGAs. ACM Trans. Embed. Comput. Syst. 13 (2), 25:1–25:26 (2013)
Papakonstantinou, A., Gururaj, K., Stratton, J.A., Chen, D., Cong, J., Hwu, W.-M.W.: High-performance cuda kernel execution on FPGAs. In: Proceedings of the 23rd International Conference on Supercomputing (ICS), pp. 515–516. ACM, New York (2009)
Dave, C., Bae, H., Min, S.J., Lee, S., Eigenmann, R., Midkiff, S.: Cetus: a source-to-source compiler infrastructure for multicores. Computer 42 (12), 36–42 (2009)
Zhang, Z., Fan, Y., Jiang, W., Han, G., Yang, C., Cong, J.: AutoPilot: a platform-based ESL synthesis system. In: Coussy, P., Morawiec, A. (eds.) High-Level Synthesis, pp. 99–112. Springer Netherlands, New York (2008)
Coutinho, J.G.F., Jiang, J., Luk, W.: Interleaving behavioral and cycle-accurate descriptions for reconfigurable hardware compilation. In: 13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, pp. 245–254 (2005)
Najjar, W.A., Bohm, W., Draper, B.A., Hammes, J., Rinker, R., Beveridge, J.R., Chawathe, M., Ross, C.: High-level language abstraction for reconfigurable computing. Computer 36 (8), 63–69 (2003)
Agility Design Solutions Inc.: Handel-C Language Reference Manual. White Paper (2007)
IEEE Comp. Society: IEEE Standard for Standard SystemC Language Reference Manual. IEEE Std 1666-2011 (2012)
Grötker, T., Liao, S., Martin, G., Swan, S.: System design with SystemC. Springer, New York (2002)
Putnam, A., Bennett, D., Dellinger, E., Mason, J., Sundararajan, P., Eggers, S.: CHiMPS: a C-level compilation flow for hybrid CPU-FPGA architectures. In: International Conference on Field Programmable Logic and Applications, pp. 173–178 (2008)
Xilinx: MicroBlaze Processor Reference Guide (2014)
Khronos OpenCL Working Group: The OpenCL Specification, Version 2.0 (2014)
Altera Corp.: Altera SDK for OpenCL: Getting Started Guide (2015)
Wirbel, L.: Xilinx SDAccel: a unified development environment for tomorrow’s data center. Technical Report, The Linley Group Inc. (2014)
Owaida, M., Bellas, N., Daloukas, K., Antonopoulos, C.D.: Synthesis of platform architectures from OpenCL programs. In: IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM 2001), pp. 186–193 (2011)
Acknowledgements
The authors would like to thank FAPESP (the Foundation to Support Research of the State of São Paulo) for the financial support provided.
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2016 Springer International Publishing Switzerland
About this chapter
Cite this chapter
de Oliveira, C.B., Menotti, R., Cardoso, J.M.P., Marques, E. (2016). A Special-Purpose Language for Implementing Pipelined FPGA-Based Accelerators. In: Drechsler, R., Wille, R. (eds) Languages, Design Methods, and Tools for Electronic System Design. Lecture Notes in Electrical Engineering, vol 385. Springer, Cham. https://doi.org/10.1007/978-3-319-31723-6_4
Download citation
DOI: https://doi.org/10.1007/978-3-319-31723-6_4
Published:
Publisher Name: Springer, Cham
Print ISBN: 978-3-319-31722-9
Online ISBN: 978-3-319-31723-6
eBook Packages: EngineeringEngineering (R0)