Abstract
This chapter reviews the challenges and designs of digital TFET circuits. Several fundamental features of TFET such as unidirectional conduction, delayed saturation, and enhanced Miller capacitance are described with emphasis on their impacts on the functionality and robustness of logic and SRAM circuits. For TFET logic circuits, structural innovations and device design are demonstrated to facilitate compact circuit design and performance improvement. For SRAM, the advantages of hybrid TFET-MOSFET 8T SRAM cell in stability and efficiency of WRITE-assisted circuit to enhance performance are addressed. Moreover, the variability and backgate bias technique for TFET digital circuit design are highlighted.
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Acknowledgement
This work was supported in part by the Ministry of Science and Technology in Taiwan under Contracts MOST 104-2911-I-009-301 (I-RiCE), MOST 102-2221-E-009-136-MY2, and MOST 103-2221-E-009-196-MY2, and by the Ministry of Education in Taiwan under the ATU Program. The authors are grateful to the National Center for High-Performance Computing in Taiwan for the software and facilities.
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Fan, ML., Chen, YN., Su, P., Chuang, CT. (2016). Challenges and Designs of TFET for Digital Applications. In: Zhang, L., Chan, M. (eds) Tunneling Field Effect Transistor Technology. Springer, Cham. https://doi.org/10.1007/978-3-319-31653-6_4
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DOI: https://doi.org/10.1007/978-3-319-31653-6_4
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