Resolving Contention for Networks-on-Chips: Combining Time-Triggered Application Scheduling with Dynamic Budgeting of Memory Bus Use

  • Kai LampkaEmail author
  • Adam Lackorzynski
Part of the Lecture Notes in Computer Science book series (LNCS, volume 9629)


One of the challenges for the design of integrated real-time systems deployed on modern multicore architectures is the finding of system configurations where all applications are guaranteed to complete their computations prior to their individual deadlines. Traditionally, timing feasability analysis, i.e., sche-dulability tests, take activation patterns and worst-case execution times (WCET) of applications as input. In the setting of mutlicore architectures with shared infrastructure, WCET are drastically overestimated as the number of accesses to a shared resource and their service times not only depend on the application itself, the service times experienced at the shared resource are significantly influenced by its use by applications executing on other cores. There are several ways to deal with the above phenomenon and give guarantees for the timing behaviour of a real-time system deployed on concurrent hardware. One either devise analysis techniques and accept the potential under-utilization of the hardware or one may employ specific protocols for coordinating the resource sharing. In this paper, we do both: (a) we combine time triggered, core-local scheduling of real-time applications with a dynamic budgeting scheme for controlling the access to the main memory bus. (b) We show how the obtained access budgets can be used at design time to ensure timing correctness at design-time. The scheme is implemented in a microkernel based operating system and we present experiments to investigate its performance.


Memory Access Active Budget Performance Counter Last Level Cache Decisive Budget 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer International Publishing Switzerland 2016

Authors and Affiliations

  1. 1.Department of Information TechnologyUppsala UniversityUppsalaSweden
  2. 2.Department of Computer ScienceTechnische Universität DresdenDresdenGermany

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