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Brain-Machine Interface pp 77–93Cite as

Neural Signal Classification Circuits

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Abstract

Robust, power- and area-efficient spike classifier, capable of accurate identification of the neural spikes even for low SNR, is a prerequisite for the real-time, implantable, closed-loop, brain–machine interface. In this chapter, we propose an easily scalable, 128-channel, programmable, neural spike classifier based on nonlinear energy operator spike detection, and a boosted cascade, multiclass kernel support vector machine classification. For efficient algorithm execution, we transform a multiclass problem with the Kesler’s construction and extend iterative greedy optimization reduced set vectors approach with a cascaded method. Since obtained classification function is highly parallelizable, the problem is subdivided and parallel units are instantiated for the processing of each subproblem via energy-scalable kernels. After partition of the data into disjoint subsets, we optimize the data separately with multiple SVMs. We construct cascades of such (partial) approximations and use them to obtain the modified objective function, which offers high accuracy, has small kernel matrices and low computational complexity. The power-efficient classification is obtained with a combination of the algorithm and circuit techniques. The classifier implemented in a 65 nm CMOS technology consumes less than 41 μW of power, and occupies an area of 2.64 mm2.

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Authors and Affiliations

  1. Delft University of Technology, Delft, The Netherlands

    Amir Zjajo

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  1. Amir Zjajo
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Correspondence to Amir Zjajo .

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Zjajo, A. (2016). Neural Signal Classification Circuits. In: Brain-Machine Interface. Springer, Cham. https://doi.org/10.1007/978-3-319-31541-6_4

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  • DOI: https://doi.org/10.1007/978-3-319-31541-6_4

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  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-319-31540-9

  • Online ISBN: 978-3-319-31541-6

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