Abstract
The new era begin to understand these beyond semiconductor CMOS devices, and circuit capabilities, to test and analysis the performance of CNTFET based structures compared to conventional silicon processes. These new devices can replace silicon in logic, analog, memory and data converters applications. The most close to the design of CNTFET based include the carbon-based options of graphene and carbon nanotube technologies, and also compound semiconductor-based Carbon nanotubes FET (CNTFETs). The study of high performance nine transistor static random access memory arrays and its optimization in 9-nm CNTFET technology are presented and comparative study done with the conventional six-transistors (6T) and previously issued eight-transistor (8T) Static RAM cell. The 9T CNTFET Static RAM cell provides same read speed comparatively 6T and 8T but has read data stability is enhanced by 1.56×. The proposed new memory cell consumes 53.40–19.17 % low leakage power comparatively the 6T and 8T Static RAM cell, respectively.
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Patel, P.K., Malik, M.M., Gupta, T. (2016). Optimization Techniques for High Performance 9T SRAM Cell Design. In: Satapathy, S., Das, S. (eds) Proceedings of First International Conference on Information and Communication Technology for Intelligent Systems: Volume 1. Smart Innovation, Systems and Technologies, vol 50. Springer, Cham. https://doi.org/10.1007/978-3-319-30933-0_28
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DOI: https://doi.org/10.1007/978-3-319-30933-0_28
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