Abstract
The modern portable devices demand ultra-low power consumption due to the limited battery size. With each new generation, the need of more transistors on the same chip is increasing due to the increased functionality. The leakage causes static power consumption is exceeding the dynamic power in the sub-nanometer designs. Therefore, effective leakage reduction technique is required to minimize the power consumption. In this paper, we have explored the existing leakage reduction techniques and propose a new leakage reduction technique that provides significant reduction in the leakage without significant area/power overhead. The simulation results on Synopsys HSPIC shows that that proposed leakage reduction technique provides 10 % reduction in leakage over the existing leakage reduction technique in the literature.
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Magraiya, V.K., Gupta, T.K., Kant, K. (2016). A Novel Leakage Reduction Technique for Ultra-Low Power VLSI Chips. In: Satapathy, S., Das, S. (eds) Proceedings of First International Conference on Information and Communication Technology for Intelligent Systems: Volume 1. Smart Innovation, Systems and Technologies, vol 50. Springer, Cham. https://doi.org/10.1007/978-3-319-30933-0_18
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DOI: https://doi.org/10.1007/978-3-319-30933-0_18
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