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International Conference on Architecture of Computing Systems

ARCS 2016: Architecture of Computing Systems – ARCS 2016 pp 293–305Cite as

Reducing NoC and Memory Contention for Manycores

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Part of the book series: Lecture Notes in Computer Science ((LNTCS,volume 9637))

Abstract

Platforms consisting of many computing cores have become the mainstream in high performance computing, general purpose-computing and, lately, embedded systems. Such systems provide increased processing power and system availability, but often impose latencies and contention for memory accesses as multiple cores try to reference data at the same time. This may result in sub-optimal performance unless special allocation policies are employed. On a multi-processor board with 50 or more processing cores, the NoC (Network On Chip) adds to this challenge. This work evaluates the impact of bank-aware and controller-aware allocation on NoC contention. Experiments show that targeted memory allocation results in reduced execution times and NoC contention, the latter of which has not been studied before at this scale.

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Acknowledgment

Tilera Corporation provided technical support of the research. This work was funded in part by NSF grants 1239246 and 1058779 as well as a grant from AFOSR via Securboration.

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Authors and Affiliations

  1. North Carolina State University, Raleigh, NC, USA

    Vishwanathan Chandru & Frank Mueller

Authors
  1. Vishwanathan Chandru
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  2. Frank Mueller
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Corresponding author

Correspondence to Frank Mueller .

Editor information

Editors and Affiliations

  1. Friedrich-Alexander University Erlangen-Nürnberg, Erlangen, Germany

    Frank Hannig

  2. Faculty of Engineering (FEUP), University of Porto, Porto, Portugal

    João M. P. Cardoso

  3. Universität zu Lübeck, Lübeck, Germany

    Thilo Pionteck

  4. Friedrich-Alexander University Erlangen-Nürnberg, Erlangen, Germany

    Dietmar Fey

  5. Friedrich-Alexander University Erlangen-Nürnberg, Erlangen, Germany

    Wolfgang Schröder-Preikschat

  6. Friedrich-Alexander University Erlangen-Nürnberg, Erlangen, Germany

    Jürgen Teich

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© 2016 Springer International Publishing Switzerland

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Chandru, V., Mueller, F. (2016). Reducing NoC and Memory Contention for Manycores. In: Hannig, F., Cardoso, J.M.P., Pionteck, T., Fey, D., Schröder-Preikschat, W., Teich, J. (eds) Architecture of Computing Systems – ARCS 2016. ARCS 2016. Lecture Notes in Computer Science(), vol 9637. Springer, Cham. https://doi.org/10.1007/978-3-319-30695-7_22

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  • DOI: https://doi.org/10.1007/978-3-319-30695-7_22

  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-319-30694-0

  • Online ISBN: 978-3-319-30695-7

  • eBook Packages: Computer ScienceComputer Science (R0)

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