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Measurement-Based Probabilistic Timing Analysis for Graphics Processor Units

  • Conference paper
Architecture of Computing Systems – ARCS 2016 (ARCS 2016)

Part of the book series: Lecture Notes in Computer Science ((LNTCS,volume 9637))

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Abstract

Purely analytical worst-case execution time (WCET) estimation approaches for Graphics Processor Units (GPUs) cannot go far because of insufficient public information for the hardware. Therefore measurement-based probabilistic timing analysis (MBPTA) seems the way forward. We recently demonstrated MBPTA for GPUs, based on Extreme Value Theory (EVT) of the “Block Maxima” paradigm. In this newer work, we formulate and experimentally evaluate a more robust MBPTA approach based on the EVT “Peak over Threshold” paradigm with a complete set of tests for verifying EVT applicability. It optimally selects parameters to best-fit the input measurements for more accurate probabilistic WCET estimates. Different system configuration parameters (cache arrangements, thread block size) and their effect on the pWCET are considered, enhancing models of worst-case GPU behavior.

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Notes

  1. 1.

    Intra-warp control flow divergence is handled with predicates/masking and NOPs.

  2. 2.

    A random variable is a variable whose value is subject to variations due to chance; it can take on a set of possible different values, each with an associated probability.

  3. 3.

    Admittedly, then the execution time is that of the modified kernel.

  4. 4.

    The same holds for deterministic approaches, which derive safe WCET estimates from incomplete system models or assumptions about the system behavior.

  5. 5.

    By extreme execution time measurements we intend execution time relatively far from the average values or relatively separated in time.

  6. 6.

    As stated in [29], p. 47: “There are many factors involved in selecting block size, and inevitably some experimentation is required.”

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Acknowledgements

Work partially supported by National Funds through FCT/MEC (Portuguese Foundation for Science and Technology) and co-financed by ERDF (European Regional Development Fund) under the PT2020 Partnership, within project UID/CEC/04234/2013 (CISTER); also by FCT/MEC and the EU ARTEMIS JU within projects ARTEMIS/0003/2012 - JU grant 333053 (CONCERTO) and ARTEMIS/0001/2013 - JU grant 621429 (EMC2); by FCT/MEC and ESF (European Social Fund) through POPH (Portuguese Human Potential Operational Program), under PhD grant SFRH/BD/82069/2011.

Author information

Authors and Affiliations

  1. ONERA, Toulouse, France

    Fabrice Guet & Luca Santinelli

  2. CISTER/INESC-TEC, ISEP, Porto, Portugal

    Kostiantyn Berezovskyi, Konstantinos Bletsas & Eduardo Tovar

Authors
  1. Kostiantyn Berezovskyi
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  2. Fabrice Guet
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  3. Luca Santinelli
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  4. Konstantinos Bletsas
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  5. Eduardo Tovar
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Corresponding author

Correspondence to Kostiantyn Berezovskyi .

Editor information

Editors and Affiliations

  1. Friedrich-Alexander University Erlangen-Nürnberg, Erlangen, Germany

    Frank Hannig

  2. Faculty of Engineering (FEUP), University of Porto, Porto, Portugal

    João M. P. Cardoso

  3. Universität zu Lübeck, Lübeck, Germany

    Thilo Pionteck

  4. Friedrich-Alexander University Erlangen-Nürnberg, Erlangen, Germany

    Dietmar Fey

  5. Friedrich-Alexander University Erlangen-Nürnberg, Erlangen, Germany

    Wolfgang Schröder-Preikschat

  6. Friedrich-Alexander University Erlangen-Nürnberg, Erlangen, Germany

    Jürgen Teich

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Berezovskyi, K., Guet, F., Santinelli, L., Bletsas, K., Tovar, E. (2016). Measurement-Based Probabilistic Timing Analysis for Graphics Processor Units. In: Hannig, F., Cardoso, J.M.P., Pionteck, T., Fey, D., Schröder-Preikschat, W., Teich, J. (eds) Architecture of Computing Systems – ARCS 2016. ARCS 2016. Lecture Notes in Computer Science(), vol 9637. Springer, Cham. https://doi.org/10.1007/978-3-319-30695-7_17

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  • DOI: https://doi.org/10.1007/978-3-319-30695-7_17

  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-319-30694-0

  • Online ISBN: 978-3-319-30695-7

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