Towards Multicore Performance with Configurable Computing Units

Abstract

Energy efficiency and the need for high performance has steered computing platforms toward customization. General purpose computing however remains a challenge as on-chip resources continue to increase with a limited performance improvement. In order to truly improve processor performance, a major reconsideration at the microarchitectural level must be sought with regards to the compiler, ISA, and general architecture without an explicit dependence on transistor scaling and increased cache levels. In attempts to assign the processor transistor budget towards engineering ingenuity, this paper presents the concept of Configurable Computing Units (CCUs). CCUs are designed to make reconfigurability in general purpose computing a reality by introducing the concept of logical and physical compilation. This concept allows for both the application and underlying architecture to be considered during the compilation process. Experimental results demonstrate that a single CCU core (consisting of double engines) achieves dual core performance, with half the area and power consumption required of a conventional monolithic CPU.