Abstract
With advances in technology scaling, circuits are increasingly more sensitive to transients caused by Single Event particles. Hardening techniques for CMOS combinational logic have been developed to address the problems associated with Single Event Transients , but in these designs, SET coupling effects have been ignored. In order to complement the Single Event Upset (SEU) hardening process, coupling effects among interconnects need to be considered in the SE Hardening of CMOS logic gates due to technology scaling effects that increase both SE vulnerability and crosstalk effects. This chapter studies hardening techniques to reduce SE crosstalk and delay effects.
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Sayil, S. (2016). Single Event Upset Hardening of Interconnects. In: Soft Error Mechanisms, Modeling and Mitigation . Springer, Cham. https://doi.org/10.1007/978-3-319-30607-0_7
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DOI: https://doi.org/10.1007/978-3-319-30607-0_7
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