Abstract
Researchers mostly considered Single Event Transients (SET) as the main cause of radiation induced transient failure of combinatorial circuits. However, recent research has reported new mechanisms for such transient failures such as radiation induced soft delays , clock jitter and race, single event crosstalk noise , delay and speed up effects. These additional sources are important, especially, for mission critical or high reliability applications such as avionics and medical system applications, and need to be included in reliability analysis. All these new mechanisms are gaining importance in newer technologies as technology scaling continues and circuit frequencies increase.
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References
B. Jacob, S.W. Ng, D.T. Wang, Memory Systems: Cache, DRAM, Disk (Morgan Kaufmann Publishers, 2007)
A. Lesea, P. Alfke, Xilinx FPGAs Overcome the Side Effects of Sub-90 nm Technology–a white paper. Technical report, Xilinx corporation, 2007
E. Normand, Single-event effects in avionics. IEEE Trans. Nucl. Sci. 43(2), 461–474 (1996)
P.D. Bradley, E. Normand, Single event upset in implantable cardioverter defibrillators. IEEE Trans. Nucl. Sci. 45(6), 2929–2940 (2004)
B.S. Gill, C. Papachristou, F.G. Wolff, in Soft Delay Error Effects in CMOS Combinational Circuits. Proceedings of 22nd VLSI Test Symposium (2004), pp. 325–330
N. Seifert, P. Shipley, M.D. Pant, V. Ambrose, B. Gill, in Radiation-Induced Clock Jitter and Race. Proceedings of the International Physics Reliability Symposium (2005), pp. 215–222
A. Balasubramanian, A.L. Sternberg, B.L. Bhuva, L.W. Massengill, Crosstalk effects caused by single event hits in deep sub-micron CMOS technologies. IEEE Trans. Nucl. Sci. 53(6) (2006)
S. Sayil, A.B. Akkur, N. Gaspard, Single Event crosstalk shielding for CMOS logic. Microelectron. J. 40(6), 1000–1006 (2009)
S. Sayil, J. Wang, S.R. Yeddula, Single Event Coupling Soft Errors in Nanoscale CMOS Circuits, IEEE Design and Test, 30(6), 1–9 (2013)
S. Sayil, A.B. Akkur, Mitigation for single event coupling delay. Intl. J. Electron. 97(1), 17–29 (2010)
P. Heydari, M. Pedram, Capacitive coupling noise in high-speed VLSI circuits. IEEE Trans. Comput. Aided Des. 24(3), 478–488 (2005)
S. Sayil, M. Rudrapati, Precise estimation of crosstalk in multiline circuits. Int. J. Electron. 94(4), 413–429 (2007)
I. Chanodia, D. Velenis, in Effects of Parameter Variations and Crosstalk Noise on H-Tree Clock Distribution Networks. IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures (2006)
M. Favalli, C. Metra, TMR voting in the presence of crosstalk faults at the voter inputs. IEEE Trans. Reliab. 53(3), 342–348 (2004)
A. Balasubramanian, O.A. Amusan, B.L. Bhuva, R.A. Reed, A.L. Sternberg, L. Andrew, L.W. Massengill, D. McMorrow, A. Sarah, J.S. Melinger, Measurement and analysis of interconnect crosstalk due to single events in a 90 nm CMOS technology. IEEE Trans. Nucl. Sci. 55(4), 2079–2084 (2008)
P.R. O’Brien, T.L. Savarino, in Modeling the Driving-Point Characteristic of Resistive Interconnect for Accurate Delay Estimation. Proceedings of the ICCAD (1989), pp. 512–515
H. Kawaguchi, T. Sakurai, in Delay and Noise Formulas for Capacitively Coupled Distributed RC Lines. Proceedings of the Asian South Pacific Design Automation Conference (1998), pp. 35–38
V. Rajappan, S. Sapatnekar, in An Efficient Algorithm for Calculating the Worst-Case Delay due to Crosstalk. Proceedings of the ICCD (2003), pp. 76–81
S. Irajpour, S. Nazarian, L. Wang, S.K. Gupta, M.A. Breuer, in Analyzing Crosstalk in the Presence of Weak Bridge Defects. Proceedings of the VLSI Test Symposium (VTS) (2003), pp. 385–392
Predictive Technology Model (PTM) (2012). http://www.eas.asu.edu/~ptm
J.M. Hutson, V. Ramachandran, B.L. Bhuva, X. Zhu, R.D. Schrimpf, O.A. Amusan, L.W. Massengill, Single event induced error propagation through nominally-off transmission gates. IEEE Trans. Nucl. Sci. 53(6), 3558–3562 (2006)
L.B. Freeman, Critical charge calculations for a bipolar SRAM array. IBM J. Res. Dev. 40, 119–129 (1996)
Q. Zhou, K. Mohanram, Gate sizing to radiation harden combinational logic. IEEE Trans. Comput. Aided Des. 25(1), 155–166 (2006)
D.C. Ness, C.J. Hescott, D.J. Lilja, in Improving Nanoelectronic Designs using a Statistical Approach to Identify Key Parameters in Circuit Level SEU Simulations. IEEE International Symposium on Nanoscale Architectures (2007), pp. 46–53
L.W. Massengill, A.E. Baranski, D.O. Van Nort, J. Meng, B.L. Bhuva, Analysis of single-event effects in combinational logic-simulation of the AM2901 bitslice processor. IEEE Trans. Nucl. Sci. 47(6), 2609–2615 (2000)
A. Maheshwari, I. Koren, W. Burleson, in Techniques for Transient Fault Sensitivity Analysis and Reduction in VLSI Circuits. Proceedings of IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (2003), pp. 597–604
A.B. Kahng, S. Muddu, E. Sarto, in On Switch Factor based Analysis of Coupled RC Interconnects. Proceedings of Design Automation Conference (2000), pp. 79–84
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Sayil, S. (2016). Single Event Soft Error Mechanisms. In: Soft Error Mechanisms, Modeling and Mitigation . Springer, Cham. https://doi.org/10.1007/978-3-319-30607-0_4
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DOI: https://doi.org/10.1007/978-3-319-30607-0_4
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