Abstract
This chapter is solely devoted to Asynchronous Assertions, meaning the sampling edge of the assertion is not a synchronous clock rather an asynchronous edge. Special focus is on pitfalls of using an asynchronous assertion both as the sampling edge as well as an antecedent expression variable.
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© 2016 Springer International Publishing Switzerland
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Mehta, A.B. (2016). Asynchronous Assertions!!!. In: SystemVerilog Assertions and Functional Coverage. Springer, Cham. https://doi.org/10.1007/978-3-319-30539-4_15
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DOI: https://doi.org/10.1007/978-3-319-30539-4_15
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Publisher Name: Springer, Cham
Print ISBN: 978-3-319-30538-7
Online ISBN: 978-3-319-30539-4
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