Abstract
Introduction: This chapter describes ‘assume’ statement and its usage for ‘static formal’ (or ‘static functional’) and ‘constrained random’ methodologies.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Author information
Authors and Affiliations
Corresponding author
Rights and permissions
Copyright information
© 2016 Springer International Publishing Switzerland
About this chapter
Cite this chapter
Mehta, A.B. (2016). ‘assume’ and Formal (Static Functional) Verification. In: SystemVerilog Assertions and Functional Coverage. Springer, Cham. https://doi.org/10.1007/978-3-319-30539-4_13
Download citation
DOI: https://doi.org/10.1007/978-3-319-30539-4_13
Published:
Publisher Name: Springer, Cham
Print ISBN: 978-3-319-30538-7
Online ISBN: 978-3-319-30539-4
eBook Packages: EngineeringEngineering (R0)