Abstract
This paper reports on a color image enhancement algorithm implemented on a reconfigurable SoC of the Xilinx Zynq family. The algorithm consists of histogram equalization followed by an unsharp masking filter. A pure software implementation running on the Zynq’s ARM Core-A9 processor is compared to several hardware-accelerated versions with respect to the design effort and the quality-of-results. The accelerators are specified at register-transfer level, at high-level (C functions) and at system-level using the recently released Xilinx SDSoC tool. The latter approach is purely software-defined and generates all the interface code and circuitry automatically. Nevertheless, experience with high-level synthesis tools and a basic understanding of hardware coprocessor principles are also required in this approach to effectively use SDSoC.
The results show that the same, significant speedup as with manual implementation can be reached for our application, but the resulting circuit tends to be larger with the higher-level design tools.
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Notes
- 1.
For more examples, consult the proceedings of the FPL (Field-Programmable Logic), ARC (Applied Reconfigurable Computing), FCCM (Field-Programmable Custom Computing Machines) or other conferences and workshops on FPGAs.
- 2.
Note that, in order to process one pixel every cycle, two BRAMs could be used alternately. Then, their values have to be added to compute the cumulative histogram. This further optimization is applicable to both the RTL and the HLS design.
- 3.
Note that automatic data reuse as defined in [14] which restructures regular loops automatically is still not implemented in commercial HLS tools as Vivado HLS.
- 4.
Note that we do not use the line-buffer objects provided by VHLS for C++ programs.
- 5.
The Zybo board also provides a 125 MHz clock for the FPGA fabric, but 125 MHz could not always be reached by VHLS.
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Weinhardt, M. (2016). Comparing Register-Transfer-, C-, and System-Level Implementations of an Image Enhancement Algorithm. In: Bonato, V., Bouganis, C., Gorgon, M. (eds) Applied Reconfigurable Computing. ARC 2016. Lecture Notes in Computer Science(), vol 9625. Springer, Cham. https://doi.org/10.1007/978-3-319-30481-6_20
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DOI: https://doi.org/10.1007/978-3-319-30481-6_20
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