Abstract
When applying FPGAs to control systems for industrial infrastructures such as thermal power plants, triple module redundancy (TMR) which is simple redundant design approaches is not enough in terms of functional safety. To cope with this problem, this paper proposes a novel dissimilar redundant design approach, focusing on the diversity offered by modern FPGA architectures. By mapping the same logic functionality to different FPGA resources, diversity is easily introduced in module redundancy using the same RTL description. In order to evaluate the effectiveness of the proposed approach, timing analysis of netlists and empirical experiments with a real FPGA chip are performed under an overclock situation as an example of common cause errors. The evaluation results show our approach effectively improves the error detection rate compared to conventional redundancy approaches.
This is a preview of subscription content, log in via an institution.
Buying options
Tax calculation will be finalised at checkout
Purchases are for personal use only
Learn about institutional subscriptionsReferences
International Electrotechnical Commission: Functional safety of electrical/electronic/programmable electronic safety related systems, IEC 61508 (2000)
Ichinomiya, Y., Tanoue, S., Ishida, T., Amagasaki, M., Kuga, M., Sueyoshi, T.: Memory sharing approach for TMR softcore processor. In: Becker, J., Woods, R., Athanas, P., Morgan, F. (eds.) ARC 2009. LNCS, vol. 5453, pp. 268–274. Springer, Heidelberg (2009)
Hayek, A., Al-Bokhaiti, M., Borcsok, J.: Design and inplementation of an FPGA-based 1oo4-archtecture for safety-related system-on-chip. In: Proceedings of IEEE 25th International Confierence on Microelectronices(ICM), pp. 1–4 (2013)
Bolchini, C., Miele, A., Santambrogio, M.D.: TMR and partial dynamic reconfiguration to mitigate SEU faults in FPGAs. In: Proceedings of 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems, DFT 2007, pp. 87–95. IEEE (2007)
Kanamaru, A., Kawai, H., Yamaguchi, Y., Yasunaga, M.: Tile-based fault tolerant approach using partial reconfiguration. In: Becker, J., Woods, R., Athanas, P., Morgan, F. (eds.) ARC 2009. LNCS, vol. 5453, pp. 293–299. Springer, Heidelberg (2009)
Konoura, H., Imagawa, T., Mitsuyama, Y., Hashimoto, M., Onoye, T.: Comparative evaluation of lifetime enhancement with fault avoidance on dynamically reconfigurable devices. IEICE Trans. Fund. Electron. Commun. Comput. Sci. 97(7), 1468–1482 (2014)
Kocur, M., Kozak, S., Dvorscak, B.: Design and implementation of FPGA-digital based PID controller. In: Proceedings of International Carpathian Control Conference (ICCC), pp. 233–236 (2014)
Lovric, T.: Systematic and design diversity—software techniques for hardware fault. In: Echtle, K., Powell, D.R., Hammer, D. (eds.) EDCC 1994. LNCS, vol. 852, pp. 307–326. Springer, Heidelberg (1994)
Zhao, Q., Ichinomiya, Y., Amagasaki, M., Iida, M., Sueyoshi, T.: A novel soft error detection and correction circuit for embedded reconfigurable systems. IEEE Embedd. Syst. Lett. 3(3), 89–92 (2011)
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2016 Springer International Publishing Switzerland
About this paper
Cite this paper
Shirakura, Y. et al. (2016). A Redundant Design Approach with Diversity of FPGA Resource Mapping. In: Bonato, V., Bouganis, C., Gorgon, M. (eds) Applied Reconfigurable Computing. ARC 2016. Lecture Notes in Computer Science(), vol 9625. Springer, Cham. https://doi.org/10.1007/978-3-319-30481-6_10
Download citation
DOI: https://doi.org/10.1007/978-3-319-30481-6_10
Published:
Publisher Name: Springer, Cham
Print ISBN: 978-3-319-30480-9
Online ISBN: 978-3-319-30481-6
eBook Packages: Computer ScienceComputer Science (R0)