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Overview of the Interconnect Problem

  • Ahmet Ceyhan
  • Azad NaeemiEmail author
Chapter

Abstract

One of the major challenges that the semiconductor industry is expected to face in the pursuit of further miniaturization of the minimum feature size in the next decade is the degrading interconnect performance. Interconnects limit the performance of integrated circuits (IC) because they add extra delay to critical paths, dissipate dynamic power, disturb signal integrity, and impose reliability concerns due to electromigration (EM) and time-dependent dielectric breakdown (TDDB). Furthermore, variations in the interconnect features during manufacturing give rise to variations in circuit performance, which makes it increasingly difficult to predict circuit behavior at ultra-scaled technology generations. The exponential increase in the number of interconnects to be routed on a microchip requires a substantial amount of effort to be devoted to design and process optimizations and increases the cost due to the increasing number of required metal levels. All of these limitations become increasingly restrictive with dimensional scaling. In this chapter, the challenges associated with integrating the conventional copper-based interconnect technology at future technology generations are described.

Keywords

Power Dissipation Metal Level Technology Node Critical Path Delay Dimensional Scaling 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer International Publishing Switzerland 2017

Authors and Affiliations

  1. 1.Intel CorporationHillsboroUSA
  2. 2.Georgia Institute of TechnologyAtlantaUSA

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