Abstract
To facilitate the integration of diverse functionality, architectural, an integrated family of circuit, device, and material level power delivery solutions are required. Per core dynamic voltage and frequency scaling is a primary concern for efficiently managing a power budget, and requires the on-chip integration of compact controllers within hundreds of power domains and thousands of cores, further increasing the design complexity of these power delivery systems. While in-package and on-chip power integration has recently became a primary concern [185, 186], focus remains on developing compact and efficient power supplies. A methodology to design and manage in-package and on-chip power has not been a topic of emphasis. Thus, power delivery in modern ICs is currently dominated by ad hoc approaches. With the increasing number of power domains, greater granularity of the on-chip supply voltages, and domain adaptive power requirements, the design of the power delivery process has greatly increased in complexity, and is impractical without a systematic methodology. The primary objective of this chapter is to describe a systematic methodology for distributed on-chip power delivery and management.
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P.-Vaisband, I., Jakushokas, R., Popovich, M., Mezhiba, A.V., Köse, S., Friedman, E.G. (2016). Intelligent Power Networks On-Chip. In: On-Chip Power Delivery and Management. Springer, Cham. https://doi.org/10.1007/978-3-319-29395-0_9
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DOI: https://doi.org/10.1007/978-3-319-29395-0_9
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