Skip to main content
SpringerLink
Log in

On-Chip Power Distribution Networks

  • Chapter
  • First Online:
On-Chip Power Delivery and Management

  • 1969 Accesses

Abstract

The impedance characteristics of a power distribution system are analyzed in the previous chapter based on a one-dimensional circuit model. While useful for understanding the principles of the overall operation of a power distribution system, a one-dimensional model is not useful in describing the distribution of power and ground across a circuit die. The size of an integrated circuit is usually considerably greater than the wavelength of the signals in the power distribution network. Furthermore, the power consumption of on-chip circuitry (and, consequently, the current drawn from the power distribution network) varies across the die area. The voltage across the on-chip power and ground distribution networks is therefore non-uniform. It is therefore necessary to consider the two-dimensional structure of the on-chip power distribution network to ensure that target performance characteristics of a power distribution system are satisfied. The on-chip power distribution network should also be considered in the context of a die-package system as the properties of the die-package interface significantly affect the constraints imposed on the electrical characteristics of the on-chip power distribution network.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Log in via an institution
Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 139.00
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 179.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD 249.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

References

  1. L.C. Tsai, A 1 GHz PA-RISC processor, in Proceedings of the IEEE International Solid-State Circuits Conference, pp. 322–323, Feb 2001

    Google Scholar 

  2. C.J. Anderson et al., Physical design of a fourth-generation POWER GHz microprocessor, in Proceedings of the IEEE International Solid-State Circuits Conference, pp. 232–233, Feb 2001

    Google Scholar 

  3. R.M. Averill et al., Chip integration methodology for the IBM S/390 G5 and G6 custom microprocessors. IBM J. Res. Dev. 43(5/6), 681–706 (1999)

    Article  Google Scholar 

  4. H.B. Bakoglu, Circuit, Interconnections and Packaging for VLSI (Addison Wesley, Reading, 1990)

    Google Scholar 

  5. L.A. Arledge Jr., W.T. Lynch, Scaling and performance implications for power supply and other signal routing constraints imposed by I/O limitations, in Proceedings of the IEEE Symposium on IC/Package Design Integration, pp. 45–50, Feb 1998

    Google Scholar 

  6. R.R. Tummala, E.J. Rymaszewski, A.G. Klopfenstein (eds.), Microelectronics Packaging Handbook (Chapman & Hall, New York, 1997)

    Google Scholar 

  7. A.V. Mezhiba, E.G. Friedman, Scaling trends of on-chip power distribution noise, in Proceedings of the Workshop on System Level Interconnect Prediction, pp. 47–53, Apr 2002

    Google Scholar 

  8. A.V. Mezhiba, E.G. Friedman, Scaling trends of on-chip power distribution noise. IEEE Trans. Very Large Scale Integr. (VLSI) Circuits 12(4), 386–394 (2004)

    Google Scholar 

  9. D.J. Herrell, B. Beker, Modeling of power distribution systems for high-performance processors. IEEE Trans. Adv. Packag. 22(3), 240–248 (1999)

    Article  Google Scholar 

  10. A. Hasan, A. Sarangi, A. Sathe, G. Ji, High performance mobile Pentium III package development and design, in Proceedings of the IEEE International Electronic Components and Technology Conference, pp. 378–385, June 2002

    Google Scholar 

  11. H. Braunisch, S.N. Towle, R.D. Emery, C. Hu, G.J. Vandentop, Electrical performance of bumpless build-up layer packaging, in Proceedings of the IEEE International Electronic Components and Technology Conference, pp. 353–358, June 2002

    Google Scholar 

  12. D. Blaauw, R. Panda, R. Chaudhry, Design and analysis of power distribution networks, in Design of High-Performance Microprocessor Circuits, ed. by A.P. Chandrakasan, W.J. Bowhill, F. Fox (IEEE Press, New York, 2001), Chapter 24, pp. 499–522

    Google Scholar 

  13. A. Dalal, L. Lev, S. Mitra, Design of an efficient power distribution network for the UltraSPARC-I microprocessor, in Proceedings of the IEEE International Conference on Computer Design, pp. 118–123, Oct 1995

    Google Scholar 

  14. M.K. Gowan, L.L. Biro, D.B. Jackson, Power considerations in the design of the alpha 21264 microprocessor, in Proceedings of the IEEE/ACM Design Automation Conference, pp. 726–731, June 1998

    Google Scholar 

  15. L. Cao, J.P. Krusius, A new power distribution strategy for area array bonded ICs and packages of future deep sub-micron ULSI, in Proceedings of the IEEE International Electronic Components and Technology Conference, pp. 915–920, June 1999

    Google Scholar 

  16. P.E. Gronowski, W.J. Bowhill, R.P. Preston, M.K. Gowan, R.L. Allmon, High-performance microprocessor design. IEEE J. Solid-State Circuits 33(5), 676–686 (1998)

    Article  Google Scholar 

  17. D.A. Priore, Inductance on silicon for sub-micron CMOS VLSI, in Proceedings of the IEEE Symposium on VLSI Circuits, pp. 17–18, May 1993

    Google Scholar 

  18. L.-R. Zheng, H. Tenhunen, Effective power and ground distribution scheme for deep submicron high speed VLSI circuits, in Proceedings of the IEEE International Symposium on Circuit and Systems, vol. I, pp. 537–540, May 1999

    Google Scholar 

  19. B.J. Benschneider et al., A 1 GHz alpha microprocessor, in Proceedings of the IEEE International Solid-State Circuits Conference, pp. 86–87, Feb 2000

    Google Scholar 

  20. A. Dharchoudhury, Design and analysis of power distribution networks in PowerPC microprocessors, in Proceedings of the IEEE/ACM Design Automation Conference, pp. 738–743, June 1998

    Google Scholar 

  21. Y.-L. Li, T.-G. Yew, C.-Y. Chung, D.G. Figueroa, Design and performance evaluation of microprocessor packaging capacitors using integrated capacitor-via-plane model. IEEE Trans. Adv. Packag. 23(3), 361–367 (2000)

    Article  Google Scholar 

  22. S.H. Hashemi, P.A. Sandborn, D. Disko, R. Evans, The close attached capacitor: a solution to switching noise problems. IEEE Trans. Adv. Packag. 15(6), 1056–1063 (1992)

    Google Scholar 

  23. B.A. Gieseke et al., A 600 MHz superscalar RISC microprocessor with out-of-order execution, in Proceedings of the IEEE International Solid-State Circuits Conference, pp. 176–177, Feb 1997

    Google Scholar 

  24. S.H. Hall, G.W. Hall, J.A. McCall, High-Speed Digital System Design: A Handbook of Interconnect Theory and Design Practices (Wiley, New York, 2000)

    Google Scholar 

  25. A. Jain et al., A 1.2 GHz alpha microprocessor with 44.8 GB/s chip pin bandwidth, in Proceedings of the IEEE International Solid-State Circuits Conference, pp. 240–241, Feb 2001

    Google Scholar 

  26. J.D. Warnock, J.M. Keaty, J. Petrovick, J.G. Clabes, C.J. Kircher, B.L. Krauter, P.J. Restle, B.A. Zoric, C.J. Anderson, The circuit and physical design of the POWER4 microprocessor. IBM J. Res. Dev. 46(1), 27–51 (2002)

    Article  Google Scholar 

  27. W.T. Lynch, L.A. Arledge Jr., Power supply distribution and other wiring issues for deep-submicron ICs, in Proceedings of the Material Research Society Symposia, vol. 514, pp. 11–27, Apr 1998

    Google Scholar 

  28. L. Zu, M. Joshi, C. Houghton, B. Loughlin, G. Vaccaro, J. Dietz, Improving microprocessor performance with flip chip package design, in Proceedings of the IEEE symposium on IC/package design integration, pp. 82–87, Feb 1998

    Google Scholar 

  29. P.D. Franzon, J.T. Schaffer, S. Lipa, A.W. Glaser, Issues in chip-package codesign with MCM-D/flip-chip technology, in Proceedings of the IEEE Topical Meeting on Electrical Performance of Electronic Packaging, pp. 88–92, Oct 1998

    Google Scholar 

  30. A. Sarangi, G. Ji, T. Arabi, G.F. Taylor, Design and performance evaluation of Pentium III microprocessor packaging, in IEEE Topical Meeting on Electrical Performance of Electronic Packaging, pp. 291–294, Oct 2001

    Google Scholar 

  31. R. Mahajan, R. Nair, V. Wakharkar, J. Swan, J. Tang, G. Vandentop, High performance package design for a 1 GHz microprocessor. Intel Technol. J. 6(2), 62–75 (2002)

    Google Scholar 

  32. T. Kawahara, SuperCSPTM. IEEE Trans. Adv. Packag. 23(2), 215–219 (2000)

    Article  Google Scholar 

  33. S.N. Towle, H. Braunisch, C. Hu, R.D. Emery, G.J. Vandentop, Bumpless build-up layer packaging, in Proceedings of the ASME International Mechanical Engineering Congress and Exposition, pp. 11–16, Nov 2001

    Google Scholar 

  34. A. Hasan, A. Sarangi, C.S. Baldwin, R.L. Sankman, G.F. Taylor, High performance package design for a 1 GHz microprocessor. IEEE Trans. Adv. Packag. 24(4), 470–476 (2001)

    Article  Google Scholar 

  35. M. Tsuk, R. Dame, D. Dvorscak, C. Houghton, J.S. Laurent, Modeling and measurement of the alpha 21364 package, in Proceedings of the IEEE International Electronic Components and Technology Conference, pp. 283–286, June 2001

    Google Scholar 

  36. P. Saxena, S. Gupta, Shield count minimization in congested regions, in Proceedings of the ACM International Symposium on Physical Design, pp. 78–83, Apr 2002

    Google Scholar 

  37. P. Saxena, S. Gupta, On integrating power and signal routing for shield count minimization in congested regions. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(4), 437–445 (2003)

    Article  Google Scholar 

  38. P. Restle, A.E. Ruehli, S.G. Walker, Dealing with inductance in high-speed chip design, in Proceedings of the IEEE/ACM Design Automation Conference, pp. 904–909, June 1999

    Google Scholar 

  39. P.J. Restle, A.E. Ruehli, S.G. Walker, Multi-GHz interconnect effects in microprocessors, in Proceedings of the ACM international symposium on physical design, pp. 93–97, Apr 2001

    Google Scholar 

  40. R.R. Troutman, Latch-Up in CMOS Technology: The Problem and Its Cure (Kluwer Academic, Boston, 1986)

    Book  Google Scholar 

  41. R. Panda, S. Sundareswaran, D. Blaauw, On the interaction of power distribution network with substrate, in Proceedings of the IEEE International Symposium on Low Power Electronics and Design, pp. 388–393, Aug 2001

    Google Scholar 

  42. M. Badaroglu, G. Van der Plas, P. Wambacq, S. Donnay, G.G.E. Gielen, H.J. De Man, SWAN: high-level simulation methodology for digital substrate noise generation. IEEE Trans. Very Large Scale Integr. (VLSI) Circuits 14(1), 23–33 (2006)

    Google Scholar 

  43. E. Salman, R. Jakushokas, E.G. Friedman, R.M. Secareanu, O.L. Hartin, Methodology for efficient substrate noise analysis in large scale mixed-signal circuits. IEEE Trans. Very Large Scale Integr. (VLSI) Circuits 17(10), 1405–1418 (2009)

    Google Scholar 

  44. D. Ozis, T. Fiez, K. Mayaram, A comprehensive geometry-dependent macromodel for substrate noise coupling in heavily doped CMOS processes, in Proceedings of the IEEE Custom Integrated Circuits Conference, pp. 497–500, Sept 2002

    Google Scholar 

  45. R. Jakushokas, E. Salman, E.G. Friedman, R.M. Secareanu, O.L. Hartin, C.L. Recker, Compact substrate models for efficient noise coupling and signal isolation analysis, in Proceedings of the IEEE International Symposium on Circuit and Systems, pp. 2346–2349, May/June 2010

    Google Scholar 

  46. R.M. Secareanu, S. Warner, S. Seabridge, C. Burke, T.E. Watrobski, C. Morton, W. Staub, T. Tellier, E.G. Friedman, Placement of substrate contacts to minimize substrate noise in mixed-signal integrated circuits. Analog Integr. Circuits Signal Process. 28(3), 253–264 (2001)

    Article  Google Scholar 

Download references

Author information

Authors and Affiliations

  1. University of Rochester, Rochester, NY, USA

    Inna P.-Vaisband

  2. Qualcomm Corporation, San Diego, CA, USA

    Renatas Jakushokas

  3. Qualcomm Corporation, San Marcos, CA, USA

    Mikhail Popovich

  4. Intel Corporation, Hillsboro, ON, USA

    Andrey V. Mezhiba

  5. University of South Florida, Tampa, NY, USA

    Selçuk Köse

  6. University of Rochester, Rochester, USA

    Eby G. Friedman

Authors
  1. Inna P.-Vaisband
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Renatas Jakushokas
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Mikhail Popovich
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. Andrey V. Mezhiba
    View author publications

    You can also search for this author in PubMed Google Scholar

  5. Selçuk Köse
    View author publications

    You can also search for this author in PubMed Google Scholar

  6. Eby G. Friedman
    View author publications

    You can also search for this author in PubMed Google Scholar

Rights and permissions

Reprints and permissions

Copyright information

© 2016 Springer International Publishing Switzerland

About this chapter

Cite this chapter

P.-Vaisband, I., Jakushokas, R., Popovich, M., Mezhiba, A.V., Köse, S., Friedman, E.G. (2016). On-Chip Power Distribution Networks. In: On-Chip Power Delivery and Management. Springer, Cham. https://doi.org/10.1007/978-3-319-29395-0_8

Download citation

  • DOI: https://doi.org/10.1007/978-3-319-29395-0_8

  • Published:

  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-319-29393-6

  • Online ISBN: 978-3-319-29395-0

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics

Search

Navigation