Abstract
Compromises between speed and power are the new semiconductor reality of the twenty first century. To support the demand for decreasing cost per function, a focus on functional diversification, on-chip integration, parallelism, and dynamic control have been adopted, posing significant circuit and system level challenges on power delivery and management in modern ICs.
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References
I. Vaisband, E.G. Friedman, Heterogeneous methodology for energy efficient distribution of on-chip power supplies. IEEE Trans. Power Electron. 28(9), 4267–4280 (2013)
S. Kose, E.G. Friedman, Distributed on-chip power delivery. IEEE J. Emerg. Sel. Top. Circuits Syst. 2(4), 704–713 (2012)
V. Kursun, E.G. Friedman, Multi-Voltage CMOS Circuit Design (Wiley, Hoboken, 2006)
P. Hazucha, T. Karnik, B.A. Bloechel, C. Parsons, D. Finan, S. Borkar, Area-efficient linear regulator with ultra-fast load regulation. IEEE J. Solid-State Circuits 40(4), 933–940 (2005)
E. Salman, E.G. Friedman, High Performance Integrated Circuit Design (McGraw-Hill, New York, 2012)
F. Waldron, J. Slowey, A. Alderman, B. Narveson, S.C. O’Mathuna, Technology roadmapping for power supply in package (PSiP) and power supply on chip (PwrSoC), in Proceedings of the IEEE International Applied Power Electronics Conference and Exposition, pp. 525–532, Feb 2010
S. Kose, S. Tam, S. Pinzon, B. McDermott, E.G. Friedman, Active filter based hybrid on-chip DC-DC converters for point-of-load voltage regulation. IEEE Trans. Very Large Scale Integr. (VLSI) Circuits 21(4), 680–691 (2013)
S. Kose, S. Tam, S. Pinzon, B. McDermott, E.G. Friedman, An area efficient on-chip hybrid voltage regulator, in Proceedings of the IEEE International Symposium on Quality Electronic Design, pp. 398–403, Mar 2012
V. Kursun, S.G. Narendra, V.K. De, E.G. Friedman, Analysis of buck converters for on-chip integration with a dual supply voltage microprocessor. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 11(3), 514–522 (2003)
M. Al-Shyoukh, H. Lee, R. Perez, A transient-enhanced low-quiescent current low-dropout regulator with buffer impedance attenuation. IEEE J. Solid-State Circuits 42(8), 1732–1742 (2007)
J. Guo, K.N. Leung, A 6-μW chip-area-efficient output-capacitorless LDO in 90-nm CMOS technology. IEEE J. Solid-State Circuits 45(9), 1896–1905 (2010)
H.-P. Le, S.R. Sanders, E. Alon, Design techniques for fully integrated switched-capacitor DC-DC converters. IEEE J. Solid-State Circuits 46(9), 2120–2131 (2011)
I. Vaisband, B. Price, S. Kose, Y. Kolla, E.G. Friedman, J. Fischer, Distributed LDO regulators in a 28 nm power delivery system. Analog Integr. Circuits Signal Process. 83(3), 295–309 (2015)
F. Lima, A. Geraldes, T. Marques, J.N. Ramalho, P. Casimiro, Embedded CMOS distributed voltage regulator for large core loads, in Proceedings of the IEEE European Solid-State Circuits Conference, pp. 521–524, Sept 2003
R.W. Erickson, M. Dragan, Fundamentals of Power Electronics (Kluwer Academic, Norwell, 2001)
C. O’Mathuna, N. Wang, S. Kulkarni, S. Roy, Review of integrated magnetics for power supply on chip (PwrSoC). IEEE Trans. Power Electron. 27(1), 4799–4816 (2012)
V. Vorperian, Simplified analysis of PWM converters using model of PWM switch. II. Discontinuous conduction mode. IEEE Trans. Aerosp. Electron. Syst. 26(3), 497–505 (1990)
V. Vorperian, Simplified analysis of PWM converters using model of PWM switch. Continuous conduction mode. IEEE Trans. Aerosp. Electron. Syst. 26(3), 490–496 (1990)
F. Wei, A. Fayed, A feasibility study of high-frequency buck regulators in nanometer CMOS technologies, in Proceedings of the IEEE Dallas Workshop on Circuits and Systems, pp. 1–4, Oct 2009
Vishay, Passive components. Available online: http://www.vishay.com
D. Lu, C.P. Wong, Materials for Advanced Packaging (Springer, New York, 2008)
International Technology Roadmap for Semiconductors. Available online: www.itrs.net/Links/2011ITRS/2011Tables/PIDS_2011Tables.xlsx
G. Palumbo, D. Pappalardo, Charge pump circuits: an overview on design strategies and topologies. IEEE Circuits Syst. Mag. 10(1), 31–45 (2010)
C. Jia, H. Chen, M. Liu, C. Zhang, Z. Wang, Integrated power management circuit for piezoelectronic generator in wireless monitoring system of orthopaedic implants. IET Circuits Dev. Syst. 2(6), 485–494 (2008)
Q. Fan, X. Fu, P. Niu, G. Yang, T. Gao, A novel low voltage and high speed CMOS charge pump circuit, in Proceeding of the IEEE International Conference on Signal Processing Systems, pp. V3–389–V3–391, July 2010
I. Vaisband, M. Saadat, B. Murmann, A closed-loop reconfigurable switched-capacitor DC-DC converter for sub-mW energy harvesting applications. IEEE Trans. Circuits Syst. I: Regul. Pap. 62(2), 385–394 (2015)
A. Shapiro, E.G. Friedman, Power efficient level shifter for 16 nm FinFET near threshold circuits. IEEE Trans. Very Large Scale Integr. (VLSI) Circuits (2015) 24(2), 774–778
R.G. Dreslinski, M. Wieckowski, D. Blaauw, D. Sylvester, T. Mudge, Near-threshold computing: reclaiming Moores law through energy efficient integrated circuits. Proc. IEEE 98(2), 253–266 (2010)
Y. Okuma, K. Ishida, Y. Ryu, X. Zhang, P.-H. Chen, K. Watanabe, M. Takamiya, T. Sakurai, 0.5-V input digital LDO with 98.7% current efficiency and 2.7-μA quiescent current in 65nm CMOS, in Proceedings of the IEEE Custom Integrated Circuits Conference, pp. 1–4, Sept 2010
K. Hirairi, Y. Okuma, H. Fuketa, T. Yasufuku, M. Takamiya, M. Nomura, H. Shinohara, T. Sakurai, 13% power reduction in 16b integer unit in 40nm CMOS by adaptive power supply voltage control with parity-based error prediction and detection (PEPD) and fully integrated digital LDO, in Proceedings of the IEEE International Solid-State Circuits Conference, pp. 486–488, Feb 2012
M. Onouchi, K. Otsuga, Y. Igarashi, T. Ikeya, S. Morita, K. Ishibashi, K. Yanagisawa, A 1.39-V input fast-transient-response digital LDO composed of low-voltage MOS transistors in 40-nm CMOS process, in Proceedings of the IEEE Asian Solid-State Circuits Conference, pp. 37–40, Nov 2011
A. Raychowdhury, D. Somasekhar, J. Tschanz, V. De, A fully-digital phase-locked low dropout regulator in 32nm CMOS, in Proceedings of the IEEE Symposium on VLSI Circuits, pp. 115–116, June 2012
J. Gjanci, M.H. Chowdhury, A hybrid scheme for on-chip voltage regulation in system-on-a-chip (SOC). IEEE Trans. Very Large Scale Integr. (VLSI) Circuits 19(11), 1949–1959 (2011)
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P.-Vaisband, I., Jakushokas, R., Popovich, M., Mezhiba, A.V., Köse, S., Friedman, E.G. (2016). Voltage Regulators . In: On-Chip Power Delivery and Management. Springer, Cham. https://doi.org/10.1007/978-3-319-29395-0_16
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DOI: https://doi.org/10.1007/978-3-319-29395-0_16
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