Abstract
In this paper , a parallel hardware implementation of a self-organizing map (SOM) is presented. Practical scalability and flexibility are the main architecture features which are obtained by using a Network-on-chip (NoC) approach for communication between neurons. The presented hardware architecture allows on-line learning and can be easily adapted for a large variety of applications without a considerable design effort. A hardware \(5\times 5\) SOM was validated through the FPGA implementation and its performances at a working frequency of 200 MHz for a 32-element input vector reach 724 MCUPS in the learning and 1168 MCPS in the recall phase.
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Abadi, M., Jovanovic, S., Ben Khalifa, K., Weber, S., Bedoui, M.H. (2016). A Scalable Flexible SOM NoC-Based Hardware Architecture. In: Merényi, E., Mendenhall, M., O'Driscoll, P. (eds) Advances in Self-Organizing Maps and Learning Vector Quantization. Advances in Intelligent Systems and Computing, vol 428. Springer, Cham. https://doi.org/10.1007/978-3-319-28518-4_14
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DOI: https://doi.org/10.1007/978-3-319-28518-4_14
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