Low-Noise and Low-Offset Operational and Instrumentation Amplifiers

Huijsing, Johan

doi:10.1007/978-3-319-28127-8_10

Johan Huijsing²

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Abstract

This chapter gives an overview of techniques that achieve low offset, low noise, and high accuracy in CMOS operational amplifiers (OA or OpAmp) and instrumentation amplifiers (IA or InstAmp). Auto-zero and chopper techniques are used apart and in combination with each other. Frequency-compensation techniques are described that obtain straight roll-off amplitude characteristics in the multi-path architectures of chopper-stabilized amplifiers. Therefore, these amplifiers can be used in standard feedback networks. Offset voltages lower than 1 μV can be achieved. Instrumentation amplifiers with capacitive coupled chopper inputs are described. They facilitate CM input voltage ranges outside the supply voltages for applications of beyond the rail current sensing.

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10.1 Introduction

The simplest type of amplifier that can be made with a low-offset voltage V_os and high common-mode rejection ratio (CMRR) is the operational amplifier (OA). But this amplifier does not have a well-determined gain. The gain of an OA is normally so high that feedback around the OA must be applied to produce an accurate result [1]. This situation is depicted in Fig. 10.1.

However, feedback destroys the CMRR because the feedback network may have unbalance and is connected to a ground reference. Therefore, other types of amplifiers have to be found to combine an accurate voltage gain, a low offset, and a high CMRR.

Instrumentation amplifiers (IA), on the other hand, can have the combination of accurate gain, low offset voltage V_os, and high common-mode rejection ratio. But they are more difficult to implement than operational amplifiers. A general symbol for an instrumentation amplifier is given in Fig. 10.2.

This chapter discusses the design of low-noise and low-offset operational amplifiers and instrumentation amplifiers:

1.
Introduction
2.
Application of IA
3.
Three-OpAmp IA
4.
Current-feedback IA
5.
Auto-zeroing
6.
Chopping
7.
Chopper stabilization
8.
Chopping + AZ or chopper-stabilized
9.
Ripple-reduction loop (RRL)
10.
Capacitive coupled input
11.
Gain accuracy of IA
12.
Summary low offset

10.2 Applications of Instrumentation Amplifiers

All applications of an IA use the combination of accurate gain and high CMRR. The first application example is a general one: to overcome a ground loop. This occurs when we want to transfer a voltage signal referred to a different ground potential V_sRef than that of the destination potential V_oRef. The situation is depicted in Fig. 10.3.

This is the case, for instance, when an instrument has to interface a sensor, like a thermocouple, that is connected to a remote ground. The small output voltage of the thermocouple requires a low offset voltage of the amplifier, while the remote ground can have a large potential difference in regard with the ground of the sensing instrument. This requires a high CMRR.

A second common application is the interfacing of the differential output voltage V_Bd of a sensor bridge that has a large common-mode voltage V_BCM, as shown in Fig. 10.4. Accuracy and low offset of the measurement in this application are of high priority.

A third application example is monitoring the voltage V_Rsd across a current-sense resistor R_s in supply lines of battery-powered systems like cell phones and laptops (see Fig. 10.5). Power management and battery life make this application rapidly more important.

A high dynamic range is required for the current-sense application, as we want to be able to measure high as well as low supply currents reasonably accurately, and do not want to spill a large amount of power across the sense resistor at high currents. This means that the sense voltage must be small and that the IA or “current-sense” amplifier needs to have a low-offset voltage under high CM input voltages. The CM input voltage range may be even far beyond its supply voltage. This thoroughly complicates the design of the IA.

A final application example is sensing of differences in voltages of skin electrodes for measuring an ECG, EEG, or EMG of a person (see Fig. 10.6). These differential voltages are in the order of 10 μV to 100 mV, while the person is capacitive coupled to large CM voltages from mains operated sources on the order of 10–100 V. High CMRR and patient safety are main requirements here.

10.3 Three-OpAmp Instrumentation Amplifiers

The most common approach to an IA is the three-OpAmp topology as shown in Fig. 10.7 (see Fig. 3.4).

The actual IA consists of an OA that is feedback by a resistor bridge network R₁₁, R₁₂, R₁₃, and R₁₄. If the bridge is in balance, the gain for differential signals is:

$$ {\mathrm{A}}_{\mathrm{d}}=-{\mathrm{R}}_{12}/{\mathrm{R}}_{11}\approx -{\mathrm{R}}_{14}/{\mathrm{R}}_{13} $$

(10.1)

To achieve a high input impedance, buffer amplifiers OA₂ and OA₃ have been placed in front of the bridge resistors. These amplifiers are connected in a non-inverting gain configuration with R₂₁, R₂₂, and R₂₃. Their extra gain is:

$$ {\mathrm{A}}_{\mathrm{d}2}=\left({\mathrm{R}}_{21}+{\mathrm{R}}_{22}+{\mathrm{R}}_{23}\right)/{\mathrm{R}}_{21} $$

(10.2)

The total voltage gain is:

$$ {\mathrm{A}}_{\mathrm{V}}=-\left({\mathrm{R}}_{21}+{\mathrm{R}}_{22}+{\mathrm{R}}_{23}\right){\mathrm{R}}_{12}/\left({\mathrm{R}}_{11}{\mathrm{R}}_{21}\right) $$

(10.3)

The main problem of the three OpAmp approach is the CMRR. In this topology the CMRR is dependent on the matching of the feedback bridge resistors, as explained in Sect. 3.2:

$$ \mathrm{CMRR}=\left(\mathrm{R}/\Delta \mathrm{R}\right){\mathrm{A}}_{\mathrm{V}} $$

(10.4)

in which ΔR/R is the relative error in one of the bridge resistors in regard to its ideal value if the bridge were balanced [2]. For instance:

$$ {\Delta \mathrm{R}}_{11}/{\mathrm{R}}_{11}=1-{\mathrm{R}}_{12}{\mathrm{R}}_{13}/\left({\mathrm{R}}_{11}{\mathrm{R}}_{14}\right) $$

(10.5)

Another shortcoming of the three-OpAmp approach is that the input CM range can not include the negative nor positive supply rail voltage. This is the consequence of the feedback connection from the output of the input buffer amplifiers OA₂ and OA₃ to their inputs. Only when a level shift is built-in in the positive input modes of these amplifiers one of the rail voltages can be reached.

10.4 Current-Feedback Instrumentation Amplifiers

The fundamentally best way to achieve a high CMRR is to convert the differential input signal V_id into a type of signal that is insensitive to the CM voltage V_iCM. Such a signal could be a magnetic signal in a transformer, or a light signal between a light-emitting and light-sensing diode. But when we stay closer to the electrical domain, also an electrical current signal could be used, if we can make it sufficiently insensitive for the CM voltage. For a circuit on a chip the last method is preferable. Therefore, the differential input voltage V_id is converted into a current and compared with the current from the conversion of the feedback part V_fb of the output voltage V_o. The architecture is called current-feedback amplifier [3], and is shown in Fig. 10.8 [4].

The first voltage-to-current converter G_m21 converts the differential input voltage V_id into a first current. The second converter G_m22 converts the feedback output signal V_fb into a second current. Both currents are subtracted and compared by a control amplifier G_m1 that drives the output voltage. A resistor divider R₂, R₁ determines the part V_fb of the output voltage V_o that is fed back. The gain of the whole amplifier will be:

$$ {\mathrm{A}}_{\mathrm{V}}=\left({\mathrm{G}}_{\mathrm{m}21}/{\mathrm{G}}_{\mathrm{m}22}\right)\left({\mathrm{R}}_2 + {\mathrm{R}}_1\right)/{\mathrm{R}}_1 $$

(10.6)

Often we can not easily make the transfer of G_m21 and G_m22 accurately different. But we can make G_m21 and G_m22 accurately equal. In that case the gain of the amplifier simplifies to:

$$ {\mathrm{A}}_{\mathrm{V}} = \left({\mathrm{R}}_2 + {\mathrm{R}}_1\right)/{\mathrm{R}}_1,\kern1em \mathrm{while}\ :{\mathrm{G}}_{\mathrm{m}21} = {\mathrm{G}}_{\mathrm{m}22} $$

(10.7)

The CMRR is now not determined by matching of main elements but just by the ratio of the Gm and small parasitic conductances, which keep the CMRR large.

A simple example of an current-feedback InstAmp is given in Fig. 10.9.

The InstAmp is Miller compensated by the capacitors C_M11 and C_M12.

The input and feedback VI converters are as simple as possible. They can be degenerated to increase the differential input voltage range if needed. Their linearity is not good in itself, but they match quite well for gain accuracy . The input CM voltage range may include the negative supply-rail voltage V_SN. This allows the output voltage V_o being referenced to V_SN. The input stages are followed by folded cascodes with a current mirror at their upper end. The push-pull output transistors are biased in class-AB by a class-AB mesh composed from M₃₉ and M₄₀ and proper bias voltages V_B5 and V_B6 (see Fig. 5.27).

A general symbol for an current-feedback IA is given in Fig. 10.10. It shows that inside the IA there are two G_m stages: one for the input G_mi and one for the feedback G_mfb.

It is interesting that the output as well as the input has a high CMRR. This means that we can connect the output reference voltage V_oRef terminal to any voltage as shown in Fig. 10.11. The voltage across the measuring resistor R_M and the current through R_M are not influenced by the voltage on V_oRef. Hence, we obtain a voltage controlled current source at the V_oRef terminal. The whole topology of Fig. 10.11 act as an accurate general-purpose V-I converter with a transconductance of 1/R_M. Hence, I_o = −V_id/R_M.

10.5 Auto-Zero OpAmps and InstAmps

In Sect. 10.2 we have seen several applications that need low offset. Auto-zeroing and chopping are the main tools to obtain low offset.

In this paragraph we start with auto-zeroing. Firstly, we will apply auto-zeroing to an OA in order to reduce its offset. Out of the many ways to implement auto-zeroing we firstly have chosen the simple method with switched capacitors at the input as shown in Fig. 10.12.

The auto-zero OA consists of an auto-zeroing input stage G_m2 with input CM control and a Miller compensated output stage G_m1.

Auto-zeroing has two phases. In phase 1 the forward path is broken, and G_m2 is being fully fed back, so that its offset appears at its input. The auto-zero capacitors C_AZ21 and C_AZ22 store this offset voltage as their inputs are short-circuited together. In phase 2 G_m2 is connected straight forward, and the auto-zero capacitors are connected to the input. Their stored offset voltage now compensates for the offset of G_m2. Therefore, G_m2 shows no offset in phase 2.

An improved auto-zero topology with storage capacitors at the output is shown in Fig. 10.13a. When the input switches S₂₁ and S₂₂ are short-circuited, and the auto-zero switches S₂₃ and S₂₄ are in auto-zero position, the output current of G_m2 charges the capacitors C₃₁ and C₃₂ at its output until the correction amplifier G_m3 compensates this current. The output of G_m2 is CM controlled at its output.

The advantage of this topology is that the capacitors can store the offset independent of the input signal. This means that the capacitors and conductance G_m3 can be taken 10× smaller for the same kT/C noise and that the compensation voltage on the storage capacitors can be taken 10× larger. The offset of G_m3 is not of interest because it is automatically taken into account in the capacitive stored voltage.

A further improvement can still be made if we replace the passive integrator capacitors for an active integrator as shown in Fig. 10.13b. The switches S₂₃ and S₂₄ do not need to be switched back and forth anymore between the virtual ground at the input of the output amplifier G_m1 and the stored compensation voltage on the capacitors C₃₁ and C₃₂, but between the two virtual grounds at the input of G_m1 and G_m3. This reduces the charge injection of the switches. For simplicity most following auto-zero circuits have been drawn with the simple circuit of Fig. 10.12.

Very important is that the auto-zero action removes offset and 1/f noise. But extra noise V_naz is added in the frequency range below 2f_AZ due to noise folding back from the bandwidth BW of the local auto-zero feedback loop. This is depicted in Fig. 10.14. Hence, it is of importance to keep this BW not too much above 2f_AZ. If the duty-cycle of the auto-zero loop is ½, the noise level is at least raised by a factor 2^1/2.

$$ {\mathrm{V}}_{\mathrm{n}\mathrm{az}} = {\mathrm{V}}_{\mathrm{n}}\left(\mathrm{white}\right)\kern0.5em {\mathrm{BW}}^{1/2}{{/\mathrm{f}}_{\mathrm{az}}}^{1/2}+{2}^{1/2}{\mathrm{V}}_{\mathrm{n}}\left(\mathrm{white}\right) $$

(10.8)

A problem is that the auto-zero OA has no continuous-time transfer. This means that when the output has to follow a ramp, a staircase with steps at the clock frequency is the result. Moreover, a factor 2^1/2 must be added to the noise as the amplifier is only used half of the time effectively. To overcome these problems the ping-pong auto-zero [5] concept of Fig. 10.15 has been invented.

In Fig. 10.15 two auto-zero input stages G_m21 and G_m22 alternately are connected between the input and the output stage in order to obtain a continuous-time solution. The stage that is not connected gets time to auto-zero itself. This allows the OA to be generally used in continuous-time feedback configurations.

We can extend the principle of ping-pong to ping-pong-pang in order to obtain a suitable InstAmp topology, as shown in Fig. 10.16 [27].

In Fig. 10.16 three auto-zero input stages G₂₁, G₂₂, and G₂₃ are used. Sequentially, two stages are connected to the output stage G_m1, while one stage is in auto-zero mode. In this way a continuous-time IA is shaped while its offset and 1/f noise is strongly reduced by auto-zeroing.

The limitation of offset reduction is due to parasitic capacitors of capacitors and switches. When the input switches change from auto-zero mode to transfer mode and vice versa, parasitic capacitors to ground are charged and discharged. Any unbalance in this charge will change the offset voltage stored on the AZ capacitors. Offline auto-zero as in Fig. 10.13a or b would therefore be preferable.

In practice the offset can maximally be reduced by a factor on the order of 100 or 1000 with auto-zeroing, reducing the offset from 10 mV to 100 μV or 10 μV.

It is very interesting to see that not only the offset voltage is reduced by the AZ function, but any CM induced differential input voltage at frequencies lower than the AZ frequency. This means that also the CMRR is drastically increased.

10.6 Chopper OpAmps and InstAmps

Before we discuss the chopper IA we will look at the chopper OA [6]. This OA is depicted in Fig. 10.17. We suppose a 6σ input offset of 10 mV for G_m2 without chopping .

The choppers Ch₂ and Ch₁ alternatively turn the signals through the input stage G_m2 straight and reverse. This means that the input voltage V_id will appear as a continuous-time current at the output. But the input offset voltage V_os2 appears as a square wave current, superimposed in the output, as shown in Fig. 10.18.

If the OA is placed in a feedback application , the input voltage will show the residual offset voltage with a low-pass filtered square wave ripple on top of it.

In the noise spectra of the offset and 1/f noise are now shifted to the clock frequency f_cl as noise and ripple, as shown in Fig. 10.19.

The resulting offset has mainly two origins: Firstly, clock skew in the chopper clocks. If the offset is 10 mV and the duty-cycle is 10⁻⁴ off, the resulting offset is 1 μV. Secondly, the resulting offset is a result of imbalance of parasitic capacitors in the choppers. The parasitic capacitors are shown in Fig. 10.20.

Suppose that chopper Ch₁ (in between the input- and output stage) has only the capacitors C_p11 and C_p12 around transistor M₁. The capacitor C_p12 produces alternative positive and negative current spikes at the output of the chopper Ch₁. This does not contribute to the offset. However, capacitor C_p11 also produces alternative spike currents at the input of chopper Ch₁. When going to the output, these alternative spike currents are being rectified by the function of the chopper Ch₁ into a DC current. An equivalent input offset voltage component can be calculated when we divide this DC current by G_m2. Fortunately, the chopper is fully balanced. Hence, charge injection from the clock in one transistor cancels that of the other. But every imbalance in layout will cause a net offset.

For chopper Ch₂ at the input (see Fig. 10.17), the capacitor C_p22 injects alternating current spikes on the clock edges. These AC current spikes are translated in rectified DC input voltage spikes across the series impedances of the chopper switch and the input signal source. Also the average DC value of these rectified spikes appear at the input as a net offset. Practical offset voltage to below 1 μV can be obtained if the chopper switches, their clock lines, and the signal lines are very carefully balanced in the layout. To further reduce the influence of the clock lines on the amplifier circuit is to layout both clock lines of a chopper within a fully shielded cable on the chip from the chopper to the clock generator in a corner.

In our quest for low offset, noise , and ripple we see two contradictory effects. On the one hand, the higher the clock frequency, the smaller the ripple at the output and the lower the 1/f noise residue. On the other hand, we see a higher residual offset caused by clock skew and charge injection at higher clock frequencies. This contradiction can be relieved by using two choppers in series for each original chopper in a nested chopper configuration [7] according to Fig. 10.21.

The inner choppers Ch₂₁₁ and Ch₁₁ can be clocked at a ten times higher frequency Cl_H than the 1/f noise corner frequency, while the outer choppers C₂₂₁ and C₁₂ are clocked at a ten times lower frequency Cl_L to take away the residual offset by the charge injection of the inner choppers. This architecture can lead to offset voltages as low as on the order of 0.1 μV. But a small ~100 μV filtered input-referred ripple at Cl_H still remains due to the original offset, and an even smaller ripple at Cl_L due to charge injection of Ch₁₁.

An other way to reduce the ripple is to combine an auto-zeroed amplifier in a ping-pong fashion with a chopper amplifier in order to obtain a low-ripple continuous-time signal transfer [8]. The block diagram is shown in Fig. 10.22a.

The choppers Ch₁ and Ch₂ chop the signal alternately positive and negative through the whole set of two ping-pong auto-zeroing amplifiers G_m21 and G_m22. The switches S₂₁₁ through S₂₂₂ and S₂₁₃ through S₂₂₄ sequentially switch the amplifiers G_m21 and G_m22 in a transfer or auto-zero mode in a full clock cycle.

The capacitors C₃₁₁ through C₃₂₂ differentially store the auto-zero correction voltages. The transconductances G_m31 and G_m32 correct the amplifiers G_m21 and G_m22 for their offsets, respectively. The auto-zero switches S₂₁₃ through S₂₂₄ switch the outputs of G_m21 and G_m22 between the stored voltages on the auto-zero capacitors and the input offset voltage of the output stage. This causes some extra charge injection. The amplifier achieves an offset of 2 μV and an input referred ripple on the order of 10 μV. The noise of the auto-zero amplifier is now transposed by the choppers to the clock frequency, which keeps the low frequencies cleaner, as shown in Fig. 10.22b.

An advantage of the ping-pong continuous-time topology is the simplicity of the frequency compensation . It is restricted to one set of Miller-compensation capacitors.

A chopper instrumentation amplifier can be constructed if we use two input stages G_m21 and G_m22, each preceded by a chopper, Ch₂₁ and Ch₂₂, respectively. This situation is shown in Fig. 10.23.

The gain is:

$$ {\mathrm{A}}_{\mathrm{v}} = \left(\left({\mathrm{R}}_1+{\mathrm{R}}_2\right)/{\mathrm{R}}_1\right)\left({\mathrm{G}}_{\mathrm{m}21}/{\mathrm{G}}_{\mathrm{m}22}\right) $$

(10.9)

The accuracy of the instrumentation amplifier fully depends on the equality of G₂₁ and G₂₂. In Sect. 10.11 we will discuss ways to increase the accuracy of G_m stages. Even with an ordinary differential pair in weak inversion, and well matched tail currents, an accuracy better than 1 % can easily be achieved without trimming.

The CMRR is also strongly increased by the chopper function for frequencies below the clock frequency. Easily 60 dB can be added to the CMRR by chopping . The improvement is limited, firstly, by the clock skew in the chopper clocks, and secondly, by unequal modulation of the charge injection spikes in the choppers as a function of the CM voltage. The resulting offset can be as low as 20 μV, which is twice that of the chopper OpAmp , and an input-referred ripple of 20 mV, which is twice of that of the OpAmps. The factor 2 is a rough simplification, and results from the fact that there are two parallel input stages.

To improve the offset and ripple, we may also apply the nested-chopper [7] principle to the chopper instrumentation amplifier , as shown in Fig. 10.24. By this a better compromise of chopper ripple and 1/f noise on the one hand and residual offset on the other hand can be achieved as explained with Fig. 10.21. An offset on the order of 0.2 μV can be achieved and a residual ripple on the order of 200 μV.

Finally, just like the chopper OA with ping-pong input stages , the chopper IA can be devised with auto-zero ping-pong-pang input stages, as explained with Fig. 10.16. This results in the circuit of Fig. 10.25. It roughly can obtain an offset Vos of 4 μV, and a ripple Vrip of 20 μV. Besides reducing offset the 2-step approach also increases the CMRR.

10.7 Chopper-Stabilized OpAmps and InstAmps

The output ripple from a chopper amplifier invites us to search for ways to reduce it. The chopper-stabilized amplifier is one of the best approaches [9]. A basic multipath nested Miller compensated OA topology is suited to incorporate chopper stabilization, as shown in Fig. 10.26a.

The basic OA is composed of two stages G_m1 and G_m2. The output stage G_m1 is differentially Miller compensated by C_m11 and C_m12. The input stage G_m2 forms the “high-frequency” path. The input stage G_m2 has an offset V_os2. When the OA is placed in a feedback loop, the offset V_os2 appears at the input.

This input error voltage V_id is now measured and corrected by the chopper amplifier’s “gain” path. This path starts with an input chopper Ch₂ that translates the input error voltage V_id into a square wave. The sense amplifier G_m5 produces a square-wave output error current proportional to V_id together with a DC output current due to its own DC offset V_os5. The chopper Ch₁ chops the square-wave error current back to a DC error current, while the DC offset current is changed into a square-wave current. The square-wave current due to offset of G_m5 is filtered and reduced by the Miller integrator capacitors C_M11 and C_M12, while the DC error current as a function of the input error voltage V_id is amplified by the DC gain of the intermediate amplifier G_m3. Finally the output current of G_m3 is being added to the output current of the input amplifier G_m2 in order to compensate its offset. It should be noted that the output CM levels of G_m2 and G_m5 have to be controlled to a CM level.

We have now obtained a two-path amplifier: a high-frequency low-gain path through G_m2, and a low-offset low-frequency high-gain path through G_m5 and G_m3. The offset can only be reduced to the extent that the high-gain path has a higher gain than the low-gain path.

The above circuit has two shortcomings: Firstly, the gain of G_m3 is only roughly 20 % of that of G_m2, as this amplifier should be able to correct the offset of G_m5 while not adding too much noise . This means that the offset is not reduced so much. Secondly, the integration function of the outer Miller capacitances C_M31 and C_M12 is not strong, particularly not at low overall closed loop gains where the overall closed bandwidth through the low-frequency path of G_m5 is larger than the clock frequency. In that case the square-wave ripple at the input has nearly the full size of the initial offset of the offset sense amplifier G_m5.

For the above reasons it is much better to step on to the multipath hybrid nested Miller compensated OA of Fig. 6.28a which has an extra integrator in the “gain path.” This circuit with chopper stabilization is given in Fig. 10.26b. The extra integrator, firstly, is able to strongly reduce the ripple, and secondly, provides much more gain. The square-wave current due to offset of G_m5 is strongly filtered out by the integrator G_m4. The integrator time constant can be chosen freely by the value of the integrator capacitors C_M41 and C_M42. The residual ripple at the output of integrator G_m4 is further reduced by the relative weak G_m3. The DC error current as a function of the input error voltage V_id is integrated and strongly amplified by the DC gain of the integrator G_m4. The integrated error voltage at the output of G_m4 is added to the output current of the input amplifier G_m2 through G_m3 in order to compensate the offset of G_m2.

One of the old struggles with chopper-stabilization is that the two poles in the gain path lead to a non-straight 6 dB per octave role-off, as shown in Fig. 10.27.

This problem can be solved in practice by applying the principle of hybrid nesting as described in Sect. 6.2 [10]. To that end we connect two differential hybrid-nested Miller capacitors C_M31 and C_M32 from the final output to the input of the integrator G_M4.

If we choose the bandwidth of the two-stage Miller-compensated HF amplifier path equal to the bandwidth of the four-stage hybrid-nested Miller loop, the overall frequency characteristic becomes straight form very low frequencies to the bandwidth of the OA. Therefore, we choose $ {\mathrm{G}}_{\mathrm{m}2}/{\mathrm{C}}_{\mathrm{M}1}={\mathrm{G}}_{\mathrm{m}5}/{\mathrm{C}}_{\mathrm{M}3} $ with $ {\mathrm{C}}_{\mathrm{M}1}={\mathrm{C}}_{\mathrm{M}11} = {\mathrm{C}}_{\mathrm{M}12} $ and $ {\mathrm{C}}_{\mathrm{M}3} = {\mathrm{C}}_{\mathrm{M}31} = {\mathrm{C}}_{\mathrm{M}32} $. The result is a straight frequency characteristic, as shown in Fig. 10.27.

The low-frequency behavior, and thus the offset of the whole amplifier is determined by that of the chopper loop. That means that we have to carefully balance the parasitic capacitors C_p11 and C_p22 of the choppers Ch₁ and Ch₂, respectively, and their lay-out. Also the duty-cycles of the chopper clocks determine the offset. If the duty-cycle is 10⁻⁴ off from 50 %, and the offset of the amplifier is 10 mV, an offset of 1 μV is resulting.

There is one more source of offset we have to watch for. That is caused by a combination of the parasitic capacitor C_p5 between the outputs of G_m5 and the offset Vos₄ of the integrator amplifier. The chopper Ch₁ chops this offset voltage up and down each chopper period on C_p5, while the chopper rectifies the associated charge current into a DC value I_p5 at the input of the integrator equal to:

$$ {\mathrm{I}}_{\mathrm{p}5}=4\kern0.5em {\mathrm{Vos}}_4{\mathrm{C}}_{\mathrm{p}5}{\mathrm{f}}_{\mathrm{cl}} $$

(10.10)

This current cannot be distinguished anymore from the DC output current of the chopper sense amplifier that is also presented at the input of the integrator. The resulting input offset V_osi is:

$$ {\mathrm{V}}_{\mathrm{osi}} = {\mathrm{I}}_{\mathrm{p}5}/{\mathrm{G}}_{\mathrm{m}5} = 4\kern0.5em {\mathrm{V}\mathrm{os}}_4{\mathrm{C}}_{\mathrm{p}5}{\mathrm{f}}_{\mathrm{cl}}/{\mathrm{G}}_{\mathrm{m}5} $$

(10.11)

The resulting offset is smaller than 1 μV referred to at the input, only if we take measures to make C_p5 small, i.e., in the order of 0.1 pF. We can always chopper-stabilize or auto-zero -stabilize the integrator amplifier to further reduce this offset term.

The input referred ripple has now been reduced by a factor 100 from a square wave of about 10 mV in the chopper amplifier into a triangular wave of about 50 μV in the chopper-stabilized amplifier. If we want to decrease the ripple further, we can auto-zero the chopper amplifier [11], as shown in Fig. 10.28.

We have now a combination of a chopper-stabilized amplifier in which the chopper amplifier is auto-zeroed. In this way the ripple can further be reduced to the 1 μV level. The noise spectrum of such an amplifier is shown in Fig. 10.29. It still suffers from noise folding and a factor 2$ {}^{\raisebox{1ex}{$1$}\!\left/ \!\raisebox{-1ex}{$2$}\right.} $ from a duty-cycle of 50 %. But at higher frequencies the HF path through G_m2 takes over and the noise reaches it thermal floor.

An interesting alternative way to reduce the ripple is using a sample-and-hold after the integrator [12], as shown in Fig. 10.30.

In this design two passive integrators have been connected as a ping-pong sample and hold with C₄₁, C₄₂, and C_H. The design is simple and elegant and has an offset of 3 μV, while the ripple is on the order of 10 μV.

Now, the step has to be made to an instrumentation amplifier. Therefore, the chopper-stabilized OA must be transformed into the current-feedback IA architecture [13]. The circuit is shown in Fig. 10.31.

The IA has a HF path through G_m21 and G_m22 and a LF gain path through G_m51 and G_m52. The LF gain path not only determines the offset and CMRR, but also sets the gain accuracy at low frequencies.

The gain at low frequencies is:

$$ {\mathrm{A}}_{\mathrm{VL}} = \left({\mathrm{G}}_{\mathrm{m}51}/{\mathrm{G}}_{\mathrm{m}52}\right)\left({\mathrm{R}}_1 + {\mathrm{R}}_2\right)/{\mathrm{R}}_1, $$

(10.12)

and at high frequencies:

$$ {\mathrm{A}}_{\mathrm{VH}} = \left({\mathrm{G}}_{\mathrm{m}21}/{\mathrm{G}}_{\mathrm{m}22}\right)\left({\mathrm{R}}_1 + {\mathrm{R}}_2\right)/{\mathrm{R}}_1 $$

(10.13)

An offset in the order of 20 μV and an output ripple of 200 μV can be obtained. The offset and ripple is a factor 2^½ larger than in the OA case because we have two input stages in parallel in both the HF and LF gain path. Also, the noise is 2^½ times larger than in the OA case.

If we want to further reduce offset and ripple the chopper amplifiers can be auto-zeroed as in the OA case [13]. The resulting block diagram is shown in Fig. 10.32.

This topology may result in an input-referred offset voltage lower than 2 μV and a ripple lower than 20 μV.

10.8 Chopper-Stabilized Chopper OpAmps and InstAmps

The smooth continuous-time chopper amplifier is the best approach to low offset. However, a 0.01 % error in duty-cycle of the clock multiplied by an initial 6σ offset voltage of 10 mV of the first stage of a CMOS amplifier presents a lower limit to the residual offset on the order of 1 μV. Moreover, the initial offset voltage on the order of 10 mV at 6σ results in an input-referred chopper square wave ripple of 10 mV. Hence, the ripple and resulting offset caused by the input amplifier must be further reduced.

The next step of improvement is to chopper-stabilize the chopper amplifier [14]. The topology is shown in Fig. 10.33.

If an amplifier has a high loop gain the differential input voltage becomes zero, except for the input offset voltage. This means in the case of the chopper-stabilized chopper amplifier of Fig. 10.33 that the right-hand side of chopper Ch₂ sees V_os2. Hence, the left-hand input side carries a square wave voltage equal to V_os2. This allows us to directly connect the correction amplifier G_m5 to the input without extra chopper. We do not need to discuss the chopper-stabilizer loop anymore, because we already discussed this at Fig. 10.26. However, there are major differences.

Firstly, the first stage of the main amplifier now determines the noise at low and high frequencies, while the correction loop determines the noise and ripple at the clock frequency.

Secondly, the hybrid nested capacitors C_M31 and C_M32 are not anymore connected to the input of the integrator, but to the input of chopper Ch₃, in order to maintain continuous negative feedback in the loop including Ch₁ [10]. This means that the parasitic capacitor C_p5, at the output of the sense amplifier, is now in parallel increased by the series connection of C_M31 and C_M32. This parallel combination of capacitors is now charged and discharged by the offset voltage V_os4 of the integrator G_m4. To avoid the extra offset of this parallel combination of capacitors in combination with V_os4, either the offset V_os4 has to be reduced, or C_M31 and C_M32 in parallel with C_p5 can be reduced by connecting them through a (folded) cascode at the output of G_m5 to chopper Ch₃.

Thirdly, the parasitic capacitor C_p2 before chopper Ch₁ is now charged and discharged to the offset voltage V_os1 of the output stage G_m1. This causes spikes at the output through the first set of Miller capacitors C_M11 and C_M12 at the size of $ {\mathrm{V}}_{\mathrm{os}1}{\mathrm{C}}_{\mathrm{p}2}/{\mathrm{C}}_{\mathrm{M}1\mathrm{S}}.\kern0.5em \mathrm{with}\kern0.5em {\mathrm{C}}_{\mathrm{M}1\mathrm{S}} = {\mathrm{C}}_{\mathrm{M}11}\kern0.5em {\mathrm{C}}_{\mathrm{M}12}/\left({\mathrm{C}}_{\mathrm{M}11}+{\mathrm{C}}_{\mathrm{M}12}\right) $. Therefore, the parasitic capacitor C_p2 at the output of G_m2 and G_m3 has to be kept small.

The offset of G_m5 causes a triangular ripple at the output of the integrator and a saw-tooth like ripple through Ch₁ at the output. This can be eliminated if the offset of the sense amplifier G_m5 is auto-zeroed similar to the chopper-stabilized amplifier of Fig. 10.28. To further reduce the offset caused by the parasitic capacitor C_p5 in combination with the offset of the integrator amplifier G_m4 this amplifier can also be auto-zero stabilized by an extra loop around it [14]. These features are shown in Fig. 10.34. In this way an offset of 0.1 μV can be achieved with a ripple lower than 10 μV. Nanosecond chopper spikes of several millivolts can still be observed at the output.

A chopper-stabilized chopper instrumentation amplifier appears when the HF and LF amplifier paths are doubled [15] according to Fig. 10.35. In contrast to the chopper-stabilized IA of Sect. 10.7, the gain in a chopper IA is not set by the ratio of G_m51 and G_m52 of the correction loop, but by the ratio of G_m21 and G_m22 of the main amplifier in cooperation with the feedback network.

$$ {\mathrm{A}}_{\mathrm{v}} = {\mathrm{G}}_{\mathrm{m}21}\left({\mathrm{R}}_1 + {\mathrm{R}}_2\right)/{\mathrm{G}}_{\mathrm{m}22}{\mathrm{R}}_1 $$

(10.14)

The reason that the sense amplifiers G_m51 and G_m52 do not determine the gain by their ratio is because their influence is shifted to the clock frequency by the choppers around the main amplifiers G_m21 and G_m22. G_m52 is sensing the feedback ripple as a result of the offset of G_m21 and G_m22. The output current of G_m52 is rectified by chopper Ch₃ and amplified by the integrator G_m4 and coupled by G_m3 to the output of G_m21 and G_m22 in order to compensate the offset of G_m21 and G_m22 in the main chopper path. The feedback signal-dependent part at the input of G_m52 is compensated for by the signal-dependent part at the input of G_m51. Therefore, the signal does not interfere with the offset cancellation.

The offset of the correction amplifiers G_m51 and G_m52 is chopped into a square wave by chopper Ch₃. The integrator does not amplify this square wave, but reduces it to a small triangular wave. Referred to the input it is translated by an attenuation of G_m3/G_m21 and a chopper Ch₂₁. This means that the shape at the input results in a small saw-tooth at the double clock frequency.

The next step to reduce the saw-tooth ripple is to auto-zero the sense stages G_m51 and G_m52 [15]. This is shown in Fig. 10.36.

The most important offset contribution of the chopper-stabilized chopper instrumentation amplifier that is left, comes from the combination of the parasitic capacitance C_p5 at the output of G_m5 in combination of the offset voltage V_os4 at the input of G_m4, see Eq. 10.11 This is particularly important as the hybrid nested Miller capacitors C_M31 and C_M32 are connected in parallel to the parasitic capacitor C_p5 at the output of G₅. To further reduce this offset component also G_m4 is auto-zeroed too, as shown in Fig. 10.36. In this way the final offset can be reduced to values well below 0.2 μV with a ripple lower than 20 μV.

It has to be kept in mind that the voltage gain of the correction loop G_m5, G_m4, G_m3 must be taken 10⁵ times larger than the voltage gain of G_m2 in order to reduce its offset from 20 mV to 0.2 μV.

10.9 Chopper Amplifiers with Ripple-Reduction Loop

The chopper-stabilized chopper amplifiers of Sect. 10.8 combine low offset, low ripple, and a straight 6 dB/octave frequency characteristic. The latter was obtained by hybrid nested Miller compensation with capacitors C_M31 and C_M32, as explained before. An interesting simplification can be made if we do not make use of this basic frequency compensation technique, but if we select a ripple-reduction notch filter to reduce the chopped offset. The notch filter will also take away signals in a small band around the clock frequency. But if we do not care about the notch for signals, for instance because we are only interested in a frequency band below the clock frequency, we can allow ripple reduction by a notch filter.

A chopper amplifier with a feedback ripple-reduction loop (RRL) [17] as a notch filter is sketched in Fig. 10.37a. The circuit senses the ripple at the output by the sense capacitors C_M31 and C_M32. The ripple currents through these capacitors are rectified by synchronous detection to DC by chopper Ch₃. The DC current is integrated by integrator G_m4 on C_M41 and C_M42, and fed back to the output current of G_m2 through an amplifier G_m3.

Waveforms of unsettled chopper ripple and sense current in the circuit of Fig. 10.37a are shown in Fig. 10.37b. The ripple at the output approaches a square wave if the bandwidth of the closed loop gain of the OpAmp is larger than the clock frequency f_c. But if the bandwidth of the closed loop gain is smaller than f_c, the output ripple looks more similar to a triangle wave.

Assuming that the polarity in the feedback RRL is correct and that the loop gain of the RRL is large enough, then the offset voltage V_os2 of G_m2 will be compensated and the ripple at the output will be reduced to nearly zero. The ripple reduction factor is equal to the DC loop gain of the ripple-reduction loop . The part of the loop through the integrator G_m4, and through G_m3 amplifies DC offset correction signals. The part of the loop between the chopper Ch₁ and chopper Ch₃ through the output amplifier G_m1 carries AC ripple signals at the clock frequency. Chopper Ch₁ together with the output amplifier G_m1 and Miller capacitors C_M11 and C_M12 can be regarded as a modulating switched-capacitor transimpedance amplifier. This converts the DC current at the input of chopper Ch₁ into a ripple voltage at the clock frequency at the output with a transimpedance of $ {\mathrm{Y}}_{\mathrm{M}1} = 2{\mathrm{f}}_{\mathrm{c}}{\mathrm{C}}_{\mathrm{M}1},\mathrm{with}{\mathrm{C}}_{\mathrm{M}1} = {\mathrm{C}}_{\mathrm{M}11} = {\mathrm{C}}_{\mathrm{M}12} $. Sense capacitors C_M31 and C_M32 in combination with chopper Ch₃ can be regarded as demodulating switched-capacitor impedances $ {\mathrm{Z}}_{\mathrm{M}3} = 1/\left(2{\mathrm{f}}_{\mathrm{c}}{\mathrm{C}}_{\mathrm{M}3}\right),\kern0.5em \mathrm{with}\kern0.5em {\mathrm{C}}_{\mathrm{M}3} = {\mathrm{C}}_{\mathrm{M}31} = {\mathrm{C}}_{\mathrm{M}32} $. They convert the output voltage ripple into a DC current that is being integrated on C_M4. The resulting voltage at the output of integrator G_m4 thus represents the average rectified output ripple. The gain from the average output ripple voltage to the integrated DC voltage at the output of G_m4 is limited to the finite DC gain A₀₄ of G_m4. The output voltage of G_m4 is converted into an offset-compensating current by G_m3. Hence, the DC loop gain A_L0 of the ripple-reduction loop and reduction factor R_r is:

$$ {\mathrm{R}}_{\mathrm{r}} = {\mathrm{A}}_{\mathrm{L}0} = {\mathrm{A}}_{\mathrm{o}4}{\mathrm{G}}_{\mathrm{m}3}/2{\mathrm{f}}_{\mathrm{c}}{\mathrm{C}}_{\mathrm{M}1} $$

(10.15)

If the factor part G_m3/2f_cC_M1 is estimated at 1, the integrator G_m4 needs a DC gain $ {\mathrm{A}}_{04} = {10}^4 $, to obtain a ripple reduction factor R_r of 10⁴.

The bandwidth B_L of the notch filter at the clock frequency equals twice the frequency f_L where the AC loop gain A_L of the ripple-reduction loop is 1. The AC loop gain is:

$$ {\mathrm{A}}_{\mathrm{L}} = \left({\mathrm{C}}_{\mathrm{M}3}/{\mathrm{C}}_{\mathrm{M}4}\right)\left({\mathrm{G}}_{\mathrm{m}3}/2\pi {\mathrm{f}}_{\mathrm{c}}{\mathrm{C}}_{\mathrm{M}1}\right) $$

(10.16)

Hence, the bandwidth B_L is:

$$ {\mathrm{B}}_{\mathrm{L}} = 2{\mathrm{A}}_{\mathrm{L}} = \left({\mathrm{C}}_{\mathrm{M}3}/{\mathrm{C}}_{\mathrm{M}4}\right)\left({\mathrm{G}}_{\mathrm{m}3}/{\uppi \mathrm{C}}_{\mathrm{M}1}\right) $$

(10.17)

In practice the bandwidth of the ripple-reduction notch filter is several kilohertz.

When we compare Fig. 10.37a with Fig. 10.33 we see that the only difference is that in Fig. 10.37a the input sense amplifier G_m5 has been eliminated. And hence, the capacitors C_M31 and C_M32 do not need to obey the rule for hybrid nesting anymore. They can be optimized for ripple sensing.

The functioning of the ripple-reduction loop (RRL) can be depicted in a simpler way if it is drawn reversed as shown in Fig. 10.37c. It clearly shows that the RRL measures the output ripple and feeds the correction signal back to correct the offset of the input transconductance G_m2.

The ripple-reduction loop cancels the ripple originating from the offset V_os2 of G_m2. There is another ripple source, which originates from the offset of V_os4 of the integrator amplifier G_m4. This is limiting the ripple reduction. The ripple originating from V_os4 can be analyzed as follows. The chopper Ch₃ switches the offset voltage V_os4 each clock cycle back and forth on the sense capacitors C_M31 and C_M32. The resulting alternating charge spikes through these capacitors are rectified by chopper Ch₃ and fed back into integrator G_m4. At the output a ripple will occur with an average square-wave or triangle-wave AC voltage V_orip equal to the offset voltage V_os4 of G_m4:

$$ {\mathrm{V}}_{\mathrm{orip}} = {\mathrm{V}}_{\mathrm{os}4} $$

(10.18)

Referred to the input this roughly results in an equivalent input ripple V_rip of:

$$ {\mathrm{V}}_{\mathrm{rip}} = {\mathrm{V}}_{\mathrm{os}4}2{\mathrm{f}}_{\mathrm{c}}{\mathrm{C}}_{\mathrm{M}1}/{\mathrm{G}}_{\mathrm{m}2} = {\mathrm{V}}_{\mathrm{os}4}{\mathrm{f}}_{\mathrm{c}}/{\uppi \mathrm{f}}_0, $$

(10.19)

in which f₀ is the bandwidth of the amplifier.

One good solution to reduce this ripple is to auto-zero the integrator. One of the many circuits that can auto-zero the integrator is shown in Fig. 10.38. For simplicity, the same auto-zero circuit is used as was used in the chopper-stabilized chopper opamp of Fig. 10.34. In fact, the only difference with the whole circuit of Fig. 10.34 is that the auto-zeroed sense amplifier G_m5 has been omitted including its sampling capacitors.

From the above chopper OpAmps with ripple-reduction loop a chopper instrumentation amplifier with RRL can easily be derived. When both sense amplifiers G_m51 and G_m52 of Fig. 10.35 are omitted the InstAmp of Fig. 10.39a, b appears.

A disadvantage of the current feedback instrumentation amplifier (CFIA) of Fig. 10.39a is that the gain is determined by the ratio of G_m21 and G_m22. As these G_m’s are normally realized by simple differential pairs the accuracy may not be better than 1 % without trimming. How to improve the gain accuracy automatically is described in Sect. 10.11.

A simple way to improve the accuracy is to go back to an OpAmp with a resistor bridge around it like described with Fig. 3.4. Without chopping , the CMRR would be not better than the inverse of the inaccuracy of the bridge multiplied by the gain setting of the bridge. But if we chop the bridge as shown in Fig. 10.39b, the average CMRR is high, while the ripple is taken away by the RRL . The limitation on the CMRR is in differences of the series resistances of the choppers. These differences are not chopped away. These differences can be seen as differences in signal source resistances which are loaded by the bridge.

Applying auto-zeroing of the integrator the simplification in Fig. 10.40 over Fig. 10.36 is even clearer, as two auto-zeroed sense amplifiers G_m51 and G_m52 are omitted.

As an alternative to the auto-zero loop around the integrator G_m4 a differential cascode buffer can be inserted between the sense capacitors C_M31 and C_M32 and chopper Ch₃ [17]. The cascode buffer needs to have a low capacitance at the chopper-side output; otherwise the ripple is not reduced so much. Also, the output offset current of the cascode needs to be made low; otherwise Ch₃ will modulate the offset current to the second harmonic of the chopping frequency, and an other type of ripple will appear at the output.

It is essential that the choppers Ch₁, Ch₂ and Ch₃ are precisely synchronized, so that there is not much delay in the amplifier stages. Otherwise the compensation does not work precise and the ripple and resulting offset is larger.

When a signal step occurs the sense capacitors C_m31,32 will punch the RRL slightly out of balance. The RRL will work to return to balance. But during this time a reducing ripple is seen at the output. When we want to get rid of this effect, one can built-in a step-sense circuit at the output, and if the step size is larger than a prescribed value, momentarily block the current through the sense capacitors by short-circuit and open-circuit switches.

When we want to eliminate the notch in the frequency characteristic further, and further reduce the chopper spikes of the chopper amplifier with RRL, one can embed it one level down in a chopper-stabilized OpAmp topology, as shown in Fig. 10.41a. The feed-forward amplifier stage G_m2 now bypasses the notch and the ripple at the higher frequencies.

The RRL can be reversely drawn for clarity, as shown in Fig. 10.41b.

In order to lower the offset and ripple of the OpAmp to the level of V_os = 1 μV and V_orip = ~10 μV (at output), respectively, the integrator G_m7 has to be auto-zeroed likewise shown in Fig. 10.2 [20].

Finely, a low-offset, low-ripple InstAmp without notch in the frequency characteristic can be devised from the above OpAmps. This is drawn in Fig. 10.42. To lower the offset and ripple to the level of V_os = 2 μV, V_orip = ~20 μV (at output) the integrator G_m7 has to be auto-zeroed. This is a better InstAmp compared with Fig. 10.32 in terms of offset, ripple, and noise [20].

10.10 Chopper Amplifiers with Capacitive-Coupled Input

There is an increasing request for interfacing high input CM voltages: Firstly, in high-voltage current-sense applications , such as power management in laptops; secondly, in solenoids of smart electro motors, for instance in electric or hybrid cars; thirdly, in biomedical sensors that make direct electrical contact to the body, as in skin electrodes or implanted devices. Of course, high-voltage transistors can be used. But often the voltage requirements are higher than the values the transistors allow. And in the case of biomedical electrodes it might be the patient safety that forbids direct contact with a transistor’s gate. Therefore, it is useful to see how we can transfer signals through on-chip metal–oxide–metal capacitors.

Figure 10.43a shows a chopper-stabilized OpAmp like that described at Fig. 10.26 with an additional chopper-capacitor-chopper combination as a chopped-capacitor coupled input. At the input the signal voltage is firstly chopped by Ch₂, next coupled through the capacitors C₂₁ and C₂₂ and finally chopped back by Ch₁ and Ch₃. The input chopper Ch₂ can be built from low-voltage CMOS transistors in an isolated N-well. Its clock can be differentially driven by two small capacitors from a grounded clock. The CM level of the clock at the chopper side has to be established by diodes coupled to the inputs. Hence, the input chopper Ch₂ can be fully capacitive isolated from ground. To avoid unbalanced signal attenuation in the capacitors C₂₁ and C₂₂ by parasitic capacitances to ground on their bottom plates, these plate sides should be connected to the input chopper Ch₂. Unbalance in combination with offset will produce an extra ripple.

At the right-hand side of the couple capacitors the CM voltage level must be established at a certain internal level V_Ref. Transistors connected as head-to-tail diodes serve to limit the CM swing at the input of the input amplifier G_m2. The high resistances of these diodes at zero V_DS softly serve to establish the level V_Ref. A firm reference level, which can cope with leakage currents and does not allow large offset, can be established either by regular resistors or by switched-capacitor resistors R_b21 and R_b22. The switched-capacitor resistors are depicted in Fig. 10.43b. On the left hand we see the resistors, and at the right hand side the switched capacitors. For a capacitor value of 5 pF, and a clock frequency of 10 kHz, we find a CM resistance of $ {\mathrm{R}}_{\mathrm{b}21} = {\mathrm{R}}_{\mathrm{b}22} = 1/\left(5\mathrm{pF}.\kern0.5em 2.10\mathrm{kHz}\right)=10\ \mathrm{MOhm}. $

The head-to-tail connected diodes serve to limit the CM swing at the input of the input amplifier G_m2. The chopper-stabilization loop with sense amplifier Gm5, Ch3, integrator Gm4, and correction amplifier Gm3 has been described with Fig. 10.26.

For lowering the 1/f noise and offset it is better to include the input amplifier G_m2 in between the two choppers Ch₂ and Ch₁. In this way a Chopper OpAmp arises, as shown in Fig. 10.44a with chopped-capacitor input. The ripple of the chopper amplifier could have been reduced by a stabilization loop like the chopper amplifier of Fig. 10.34. But then we need to also capacitive couple the sense amplifier G_m5 to the input, for instance as it was done in Fig. 10.35. To avoid this extensive circuitry we rather completely eliminate the sense amplifier and keep only a ripple-reduction loop as explained with Fig. 10.37a. We have to keep in mind, though, that elimination of the sense amplifier produces a notch in the frequency response at the clock frequency.

The signal through the coupling capacitors C₂₁ and C₂₂ will be attenuated by their load with parasitic capacitors like in the circuit of Fig. 10.43a. To keep the attenuation minimal and balanced, we should connect the bottom plates of the oxide isolated coupling capacitors to the input side, and take care that the parasitic capacitors of the diodes are small and balanced enough. To further reduce the ripple we can take all measures as explained in Sect. 10.9.

It is just interesting to draw Fig. 10.44a little different with the ripple-reduction loop from the output side back to the input of chopper Ch₁. This is shown in Fig. 10.44b. It looks simpler to understand.

After the discussion of OpAmps with chopped-capacitor input coupling, it is easy now to make the step to instrumentation amplifiers. Figure 10.45 shows a chopper-stabilized InstAmp with chopped-capacitor input coupling. The input capacitors C₂₁₁, C₂₁₂, C₂₂₁, and C₂₂₂ together with the input choppers Ch₂₁ and Ch₂₂ make up a chopped-capacitor bridge InstAmp like the resistor-bridge InstAmp of Fig. 3.4. The closed-loop gain can be set either by the ratio of (C₂₁₁, C₂₁₂)/(C₂₂₁, C₂₂₂) or by the feedback attenuator $ {\mathrm{R}}_1/\left({\mathrm{R}}_1 + {\mathrm{R}}_2\right) $. Unbalance in the input capacitors will not so much deteriorate the CMRR, as it did in the bridge InstAmp of Fig. 3.4, because the whole capacitor bridge is being chopped. The input impedance of this InstAmp will not be very high as a result of the chopped-capacitor bridge at the input. For C₂₁₁ and C₂₁₂ of 10 pF, and a clock frequency of 10 kHz, the input impedance R is $ 1/\left(10\mathrm{pF}.\mathrm{2.10}\mathrm{kHz}\right)=5\ \mathrm{MOhm} $. As this value is not so high an unbalance of the impedances in the input signal source attenuated by the input impedance of the amplifier may cause a slightly lower CMRR.

In line with the OpAmp of Fig. 10.44a it is better to include the input amplifier G_m2 in-between the two choppers Ch₂ and Ch₁ for lowering its 1/f noise and offset. In this way a chopper InstAmp arises, as shown in Fig. 10.46a with chopped-capacitor input. Like in Fig. 10.44b ripple-reduction loop has been used to lower the chopper ripple. The CMRR will remain high by the chopping of the whole capacitor bridge, and only restricted by the loading of possible unbalanced source resistances as in the circuit of Fig. 10.45.

It is interesting to see that we can replace the chopped-capacitor bridge by a chopped-resistive bridge followed by capacitive coupling, as shown in Fig. 10.46b to obtain the same goal. The coupling capacitors C₂₁ and C₂₂ isolate the CM voltage of the bridge mid points from ground. Now the transfer function of the bridge between input and output is determined by resistors. This topology can be used to our advantage if the resistors can be made more accurate or more linear than capacitors. A further advantage is that the capacitive peak charge currents with full capacitive coupling are absent. A disadvantage is that the choppers now are loaded by a resistive bridge. The chopper series resistances may deteriorate the bridge accuracy. Moreover, the resistive bridge creates more noise. The CMRR remains high due to the chopping of the whole bridge.

To increase the input impedance it is better to step away from the bridge-type InstAmp and go to the current-feedback InstAmp. This topology is presented in Fig. 10.47 in combination with chopped-capacitor input coupling. The input impedance of in the InstAmp of Fig. 10.47 will now be made up by the chopped parasitic ground-plate capacitances at the chopper side of the input capacitances C₂₁₁, C₂₁₂, C₂₂₁, and C₂₂₂, and the parasitic ground capacitors of the elements following. If we suppose that the input capacitances have a value of 10 pF, and the parasitic ground capacitances 1 pF, we can expect an input chopped-capacitor resistance of $ 1/\left(1\mathrm{pF}.\mathrm{2.10}\ \mathrm{kHz}\right)=50\ \mathrm{MOhm} $.

A disadvantage of the circuit of Fig. 10.47 is that the accuracy can be deteriorated, firstly, by inequality of G_m21 and G_m22 (cures for this inaccuracy are presented in the next paragraph), secondly, if the parasitic ground capacitances that load the coupling capacitances are not well matched.

The last circuit that will be discussed here is the Chopper InstAmp with Chopped-Capacitor input and Ripple-Reduction Loop and with Biomedical Electrode offset voltage compensation of Fig. 10.48. A basic problem of biomedical electrodes is that they may generate a DC offset of several 100 mV, while AC voltages of the order of μV have to be measured. A natural solution would be to couple these electrodes by capacitors. However, if we want to measure signals from a well determined frequency of 1 Hz and higher, and the input resistance of the amplifier can be reliably made 100 MΩ, then we still need 10 nF input coupling capacitors. And those can not be easily integrated on chip. Therefore, an additional integrator loop following the output is made with a large time-constant. It uses a special chopped-capacitor integrator [19] depicted as G_m7 and G_m6. At the output of that integrator a compensation voltage V_DCcomp will appear that will increase proportionally to the offset. This compensation voltage will be fed through a third input chopper Ch₂₃ into C₂₃₁ and C₂₃₂ to compensate the DC offset at the input. As a basis the InstAmps of Fig. 10.46a or Fig. 10.47 can be used. For simplicity we have chosen Fig. 10.46a. The offset that can be cancelled is limited by the supply voltage.

10.10.1 Wide-Band Chopper Amplifiers with Capacitive-Coupled Input

The aforementioned chopper amplifiers with the capacitive-coupled input of Figs. 10.43, 10.44, 10.45, 10.46, 10.47, and 10.48 all show a notch in their amplitude characteristic at the chopping frequency. This notch occurs because an input signal at the chopping frequency is down-converted to DC by the input chopper and subsequently blocked by the high-pass filter of the coupling capacitors connected to the bias resistors behind them. This not only affects the flat frequency characteristic but also results in a slow-settling ripple at the chopping frequency as a response to an input signal step. Furthermore, as all these amplifiers are used in feedback loops, an insufficiently controlled chopper ripple up-swing can occur due to the zero loop gain at the notch frequency.

Consequently, these amplifiers are only suitable for applications where the signal bandwidth is lower than the chopping frequency and where there are no fast settling requirements. However for wide-band applications, where fast settling is required, another approach is necessary which maintains a flat frequency response over the entire band of interest including the chopping frequency. This type of approach calls for dual signal paths.

In the first approach, shown in Fig. 10.49, an operational amplifier combines a high-frequency (HF) path, including the chopper frequency, with a precision DC path [23, 28].

The circuit of Fig. 10.49 can be seen as being derived from the chopper-stabilized operational amplifier of Fig. 10.26b. The difference here is that coupling capacitors have been inserted both directly into the HF path, and into the DC path behind Ch₂. Also, chopper Ch₂ has been replaced by a fully floating chopper with a wide CM input voltage range able to follow the CM range of the input signal. Its driver clock has been coupled in a capacitive way. This will be dealt with in the next section on fully floating capacitive-coupled input choppers. Chopper amplifier G_m5 has yet to be auto-zeroed, chopper-stabilized, or given a ripple-reduction loop to reduce the output ripple caused by the offset V_os5 of G_m5. The hybrid-nested Miller compensation scheme (see Fig. 6.28a) with G_m2 and C_M11, C_M12 and G_m5 and C_M31, C_M32 ensures a flat frequency characteristic, under the condition that the ratios of G_m2/C_M1 and G_m5/C_M3 are taken equally, with C_M1 equal to the series connection of C_M11 and C_M12, likewise C_M3 equal to the series connection of C_M31 and C_M32.

The CM input level of the amplifiers G_m2 and G_m5 is set by four large resistors R_b to a reference voltage V_Ref. Head-to-tail connected diodes across these resistors prevent excess voltages at the inputs of G_m2 and G_m5 during the edges of large input voltage steps. The input offset voltage V_os2 of G_m2 is compensated by the output current of G_m3 at the current summing point of G_m2 and G_m3, which is at the output of the DC path. The reduction factor by which the offset is reduced is determined by the voltage gain ratio of A_m5 × A_m4 × G_m3/G_m2. The transconductance G_m3 is normally taken five times lower than G_m2 to prevent it from increasing the noise of G_m2 too much, while still allowing it to compensate an offset related to 20 % in the full output current range of G_m2. Therefore, if we want to decrease the offset of G_m2 by a factor of 10⁴ we have to be sure that the voltage gain A_m5 × A_m4 is more than 5 × 10⁴.

A disadvantage of the circuit in Fig. 10.49 is that due to the capacitive coupling there is no overall DC feedback on the offsets V_os2 and V_os5. Hence, these offsets are amplified open loop, and independent of the closed loop gain. For V_os2 the chopper stabilization loop through G_m5 will take care, as we have already seen. However, the output ripple caused by V_os5 is only suppressed by the integrator G_m4 and the Miller compensation capacitors around G_m1. The ripple still has to be reduced by auto-zeroing or chopper-stabilize G_m5, or with a ripple-reduction loop around G_m5, as shown in [23]. A simple yet effective way to turn the open loop gain of these offsets into a closed loop gain, and thus to further reduce the offset and ripple, is shown in the second approach of Fig. 10.50 [24].

A third chopper Ch₃ has been inserted between the high-frequency and low-frequency paths behind the coupling capacitors. This chopper, firstly, restores a DC coupling between the circuit input and the input of G_m2 by down-converting the signal from the up-converting chopper Ch₂ and the coupling capacitors C₅₁, C₅₂. Secondly, it measures the output chopper ripple through the HF coupling capacitors C₂₁, C₂₂ and rectifies the ripple synchronously to DC, compensating the offset voltage V_os5 that causes the ripple. To reduce the output ripple further, G_m5 still has to be either auto-zeroed (see Fig. 10.28) or chopper-stabilized, otherwise a ripple-reduction loop can be applied.

From the operational amplifier of Fig. 10.50 a capacitive-coupled bridge-type instrumentation amplifier can be made simply by adding two sets of input coupling capacitors C₃₁, C₃₂ and C₄₁, C₄₂ along with an input chopper Ch₄. The circuit is shown in Fig. 10.51 [24].

Now, however, this version has two capacitive bridges at its input: C₂₁, C₂₂ and C₃₁₁, C₃₂ for higher frequencies, and C₄₁, C₄₂ and C₅₁, C₅₂ for low frequencies. The high-frequency bridge functions as the resistive bridge in the instrumentation amplifier of Fig. 10.7. The input impedance is equal to the inverse of the product of the input capacitance and four times the clock frequency. Furthermore, this bridge restricts the CMRR in the high-frequency path to the product of gain A_v = C₃₁/C₂₁ = C₃₂/C₂₂ and the inverse relative imbalance C/ΔC of the bridge, as expressed in Eq. 10.4. For the low-frequency bridge on the other hand, the imbalance is averaged out by the choppers Ch₂ and Ch₄ at its input, which results in the CMRR also being restored.

To overcome these disadvantages, an option is to isolate the CM voltage of the input path from that of the feedback path. This can be achieved by giving each path with their coupling capacitors its own G_m stage with a good CMRR. This results in the capacitive-coupled current-feedback instrumentation amplifier of Fig. 10.52. Giving each path with their coupling capacitors a G_m stage also drastically improves the input impedance for both the input path as well as for the feedback path. However, differences in the nonlinearity of the two sets of G_m’s may lead to more harmonic distortion. Some measures, as discussed in Sect. 10.11, may help to make the G_m’s more equal.

Besides the class of chopper-stabilized amplifiers, a class of chopper-stabilized chopper amplifiers also exists, as we have seen in Sects. 10.7 and 10.8, respectively. Chopper-stabilized chopper amplifiers have a lower offset, since these amplifiers already have a chopper amplifier core which is further enhanced by chopper stabilization. The same holds for the capacitive-coupled versions. In Fig. 10.53 a capacitive-coupled chopper-stabilized chopper amplifier is shown.

Similarly to the circuit of Fig. 10.49, the offsets of G_m2 and G_m5 are processed open loop to the output. Therefore, we also insert a chopper Ch₄ between the HF and LF coupling capacitors, deriving Fig. 10.54.

The high-frequency path with amplifier stage G_m2 is now inserted between the input and output choppers Ch₂ and Ch₁, respectively. The offset voltage V_os2 of G_m2 produces an offset current at its output that is transformed into a square-wave ripple current by chopper Ch₁. This ripple is integrated by the Miller-compensated output stage G_m1 and presented at its output in the shape of a triangular voltage ripple. An external feedback loop feeds the output voltage ripple into the input. Amplifier stage G_m5 in the DC path senses this voltage ripple at the input and transforms it into a ripple current at its output. Chopper Ch₃ synchronously detects this ripple current of G_m5 and transforms it into a DC error current. Integrator G_m4 integrates the error current and builds up an error voltage at its output. Finally, the correction amplifier G_m3 corrects the offset current of G_m2 by adding its output current to that of G_m2. In this way the offset of G_m2, from which the ripple originates, is sufficiently corrected, depending on the loop gain of this process. The transconductance G_m3 is chosen small enough, for instance G_m2/5, that it does not add much noise to that of G_m2, but large enough that it is able to correct the worst case offset of G_m2.

There are still two remaining obstacles. Firstly, the offset V_os5 of G_m5 is chopped by Ch₃ into another ripple. Although this ripple is suppressed by integrator G_m4 and the Miller-compensated output stage G_m1, we still want to suppress it further. This can be done by auto-zeroing or chopper-stabilizing of G_m5, which has already been shown in the circuit of Fig. 10.34. Secondly, the offset of G_m4 limits the effectiveness of the ripple reduction because that offset appears as a square wave at the input of chopper Ch₃. There it charges and discharges all present parasitic capacitors including the hybrid nesting capacitors C_M31, C_M32 (see Fig. 6.28a). This square wave cannot be effectively distinguished from the output voltage ripple, as these two are related by C_M31, C_M32. Therefore, we want to lower the offset voltage of G_m4. This can be done by auto-zeroing or chopper stabilization, as also explained together with Fig. 10.34.

As with the chopper-stabilized amplifier, we can transform the chopper-stabilized chopper amplifier into an instrumentation amplifier by adding two capacitive bridges between its input and feedback path. This is shown in Fig. 10.55. The negative-feedback bridge restricts the input impedance to the inverse of the product of the input capacitance and 4 times the clock frequency. Moreover, the bridge now restricts the CMRR in the low-frequency path to the product of gain C₃/C₂ and the inverse relative imbalance C/ΔC of the bridge, as expressed in Eq. 10.4.

To improve the input impedance and CMRR both the input and feedback paths with their coupling capacitors can be given their own subsequent G_m stage. In this way a capacitive-coupled chopper-stabilized current-feedback chopper instrumentation amplifier arises, as shown in Fig. 10.56. However, differences in the nonlinearity of the two sets of G_m’s may result in more harmonic distortion. Some measures, as discussed in Sect. 10.11, may help to make the G_m’s more equal.

10.10.2 Fully Floating Capacitive-Coupled Input Choppers

In current-sensing applications for battery management in laptops and motor management in electric cars, we need to sense small voltages of several to tens of millivolts across a current-sense or shunt resistor at CM voltages of 10–100 V. For electric motors the CM voltage could even become negative by inductive kick back. In the previous section we saw how capacitive coupling would allow these applications. We only have to build fully floating choppers in front of the coupling capacitors which can accommodate the large input CM-voltage range reaching beyond the positive and negative supply-voltage rails [25]. To realize these fully floating choppers we have three requirements to fulfill: (1) The chopper transistors need to be floating within a large CM-voltage range beyond the supply-rail voltages. (2) A chopper clock has to be delivered to the chopper transistors in a floating way, preferably by-on chip high-voltage capacitors. (3) The coupling capacitors at the signal output should be able to isolate large voltages between their plates and be linear. Figure 10.57 shows a basic circuit that can facilitate these requirements.

The four N-channel transistors are each built in a P-well. Each P-well is isolated from the P-substrate by an N-buried layer. Each P-well is connected to its source and driven from an input. The P-substrate is connected to ground. The N-buried layers are left floating to facilitate large (beyond the supply rails) positive and negative voltages on the P-wells. Potential latch-up issues associated with the parasitic NPNP (N-source, P-well, floating N-buried layer, P-substrate) structure of the NMOS transistors can be circumvented by two measures. Firstly, a connection between source and P-well will prevent the upper NP-diode from conducting. Secondly, a HV clamping diode between the positive supply and the floating N-buried layer will prevent this N-pocket from dropping below the P-substrate, which means that the lower NP-diode cannot turn on [26].

When the CM input voltage rises to higher positive levels, the CM voltage of the N-MOS transistors also rises to higher positive levels together with their connected P-wells. The P-wells take up the N-buried layers by the PN diodes between them. Hence, the IC process should allow a high voltage between the N-buried layer and the P-substrate. When the CM input voltage sinks to levels below that of the substrate the voltage on the P-wells sinks below the N-buried layers. This means that the IC process should allow a high negative voltage between the P-wells and the N-buried layers. The N-buried layers are prevented from sinking below the P-substrate by the HV diode clamps connected to the positive supply, as explained before.

The floating driver clock is realized by connecting small (0.1 pF) coupling capacitors between the chopper clock and the gates of the chopper transistors. High-voltage and linear signal-coupling and clock-coupling capacitors can be realized in many IC-processes by an interwoven metal finger layout with oxide isolation in between.

The CM levels of the gates have to be fixed in relation to those of their sources. The simplest approach to fix the CM levels is using sets of diode clamps. This is shown in Fig. 10.58.

Reverse clamp diodes D_r11 through D_r41 prevent the gate voltages of the 4 chopper transistors from going lower than one diode voltage below their source voltages. This determines the lower clock voltage level on their gates. Forward chains of clamp diodes D_f11–D_f1x through D_f41–D_f4x prevent the gate voltages from going higher than two or more diode voltages above their source voltages. If we choose three diodes in the forward chain, then we can have a clock amplitude of four diode voltages, providing an effective drive voltage over the threshold voltage of the chopper transistors of two diode voltages. The peak-to-peak clock amplitude should always be kept lower than the sum of the reverse and forward diode voltages. This rule should also be obeyed over the ambient temperature range. If the clock amplitude becomes too large, the diodes conduct at the clock edges, and injection-current peaks occur at the input terminals.

At sudden positive input surges the built-in back-gate diodes D_DB (dotted) of the chopper transistors protect the chopper transistors against large source–drain voltages. Incidentally, these back-gate diodes limit the maximum differential input voltage to one diode voltage. For higher differential voltages, some will conduct. Sudden negative surges require the insertion of the diodes D_o1 and D_o2 between input and output to limit the drain–source voltage of the low-voltage chopper transistors.

A disadvantage of using passive clamping diodes, besides all these diodes having parasitic capacitors, is that we always lose one additional diode voltage. Therefore, it is better to use active clamps instead of passive diode clamps so that no diode voltage will be lost. A basic circuit for an active clamp is a latch. A basic floating chopper circuit that uses active clamps is shown in Fig. 10.59. The active clamp transistors M_N5−M_N8 are also made with floating N-wells so that they are capable of beyond-the-rail operation.

When the Clk_p edge goes high and Clk_n edge low, the NMOS latch transistors M_N6 and M_N8 start to conduct. They shortcut the gates of the cross-chopper transistors M_N3 and M_N4 to their sources so that these transistors are opening. At the same time the latch transistors M_N5 and M_N7 become non-conducting and their drain–source voltages become high. This activates the gates of the straight chopper transistors M_N1 and M_N2 so that they turn on. The chopper now conducts the input signal straight forward. We see that the latches are quite helpful. First of all, they facilitate a fast and simultaneously positive and negative clock switching behind the coupling capacitors. Secondly, they position the negative voltage levels of the clock and clock-bar behind the coupling capacitors at the input level so that the full clock amplitude is efficiently used to open and close the chopper switches. Another advantage of using the latches is that the amplitude of the clocks can now be freely chosen on the basis of the optimal voltage to switch on the chopper transistors. The amplitude is not restricted by diode clamps. The coupling capacitors chosen for the clock should preferably be as small as possible, but still large enough that the gate capacitors of the chopper switches do not reduce the clock amplitude too much. Practical values in the order of 0.1 pF have been used.

Still many precautions have to be taken to protect the low-voltage chopper switches. This is shown in Fig. 10.60.

Besides the capacitive coupling and active latches the floating chopper of Fig. 10.60 shows other measures to protect the chopper transistors. Again the built-in back-gate-to-drain diodes D_DB1 through D_DB4 protect the chopper switches when a sudden upward input CM surge occurs. Additional diodes D₁ and D₂ between input and output are inserted for protection during a sudden downward input CM surge. Incidentally, these diodes limit the maximum differential input voltage to that of a diode voltage. The drain-to-back-gate diodes of M_N5 through M_N8 protect the chopper gates during a sudden positive CM input surge. A series chain of diodes between the drains and sources of M_N5 through M_N8 could protect the chopper gates at a sudden negative CM input surge, even if the clock signal is absent and the latches are inactive. However, in our circuit we have chosen to protect the chopper gates with small active circuits. If a negative CM input transient occurs, both the capacitors C₁₃ and C₂₃, which are equal to the other driver capacitors, and diodes M_N11 and M_N14 “feel” the CM movement on the driver capacitors and mirror the associated current through M_N10, M_N12, M_N13, and M_N15 back into the driver capacitors so that the gate side of the driver capacitors are accordingly following down. Lastly, relatively small series resistors have been inserted in the lines connecting to the inputs in order to reduce clock spikes in the input signals. Clock spikes at the input can also be kept small if we choose the driver clocks flash, meaning that the ascending edge of one clock line occurs simultaneous with the descending edge on the complementary clock-bar line. In that way the positive charge injection and negative charge injection in the chopper switches largely compensate each other.

We can simplify the circuit of Fig. 10.60 to that of Fig. 10.61 by using only one input as a reference for all input chopper transistors. Of course this brings imbalance to the on-voltages of the chopper switches. What is more, the chopper response may show more second harmonics. However, when the differential input voltage is small the imbalance is low, and the spurious responses might be negligible, while keeping the circuit simpler.

In some cases, such as in an instrumentation amplifier or in an ADC, we need to chop differential input voltages larger than a few hundred mV. The built-in diodes in the chopper transistors between their P-well back-gates and N-doped sources and drains prohibit the previously described floating choppers from processing differential voltages larger than several hundreds of mV. Nonetheless, if we are able to keep the back-gates at any moment on the lowest voltage present in the chopper, this limitation is eliminated. To that end a minimum selector with MNS1 and MNS2 (see Fig. 10.62), has been inserted between the input terminals with its minimum point connected to all back-gates. If the voltage at the positive input terminal is higher than that at the negative one, MNS2 conducts and connects the minimum point to the negative input terminal. If the voltage on the negative input terminal is higher than that of the positive one, MNS1 conducts and connects the minimum point to the positive input terminal. In any case the minimum point is connected to the lowest input voltage.

Figure 10.62 shows the full circuit of a floating chopper with capacitive-coupled driver clocks and protection by active latches and diode clamps that can handle 2 V differential input voltages, limited by the protection diodes. It is further explained in [26]. To protect the floating chopper transistors from large positive and negative CM input surges, two antiparallel diode chains DC1 and DC2 have been placed across the chopper between the positive input and output, and another two antiparallel diode chains DC3 and DC4 have been placed between the negative input and output. For protection against large positive and negative DM surges two antiparallel diode chains DC5 and DC6 have been connected between the two input terminals.

If we want to chop even larger differential voltages, the limitation by the back-gate diodes can be removed by using two anti-series-connected transistors for each chopper transistor. A basic sketch for this floating chopper is given in Fig. 10.63. If MN1, MN11 and MN2, MN12 are turned on, the floating chopper connects straight forward. Even if the differential signal is +5 V, the switched-off transistors MN13 and MN4 block the cross path. Their back-gates are not turned on. In each straight and cross path there are always two transistors that block a large positive or negative differential voltage. It stands to reason that the chopper transistors must be able to carry 5 V between their drains and sources. Protection circuitry still has to be added around the high-differential-voltage floating chopper of Fig. 10.63.

10.11 Gain Accuracy of Instrumentation Amplifiers

The inaccuracy of current-feedback instrumentation amplifiers is proportional to the relative difference in G_m of the input stage and feedback stage. The input stages are drawn in Fig. 10.64. For accurate matching the transistors need to be large. For high CMRR and for a high signal-to-noise ratio the input transistors need to have the highest possible G_m. This means they have to be biased in weak inversion with a relative large width/length ratio. Also the current sources I_T1 and I_T2 need to be matched well, as the G_m of the differential input transistor pairs is dependent on their tail current. Therefore, the current-source transistors need to be made less sensitive to differences in their gate-source threshold voltages by biasing them in strong inversion using long transistors, or in weak inversion in combination with degeneration resistors.

The most used input stage is of the P-Channel type for two reasons: Firstly, P-Channel transistors always have an isolated back gate. This makes it possible to bootstrap the back gates with the source voltages. By this measure the input G_m is much less dependent on the input CM voltage. This raises the CMRR from about 50 to 80 dB. Secondly, P-Channel transistors have less 1/f noise than N-Channel transistors. Folded cascodes behind the input stage allow the input CM voltage to include the negative rail, and increase the voltage gain of the input stage.

To further increase the CMRR of the input stages the input transistors have been cascoded in Fig. 10.65. This can be easily done if transistors are available with two different threshold voltages. For the input transistors we use the higher threshold transistors, and for the cascode transistors the lower threshold transistors. In that way both transistors function in saturation at high voltage gain. Cascoding of the input transistors also helps to decrease the gain dependency of G_m to the CM voltage.

For the same reason the tail-current source transistors should be cascoded. We can even improve further if we built up the tail-current source with the same transistor combination as that of the differential pair and keep the elements at the same current density, the impedances of tail current and input transistors will compensate each other. This results in a higher CMRR and lower CM dependency of G_m.

In the next examples the input transistors are degenerated in order to improve the accuracy. This ultimately increases the supply current over square noise voltage ratio of the input stages . But sometimes this is the easiest.

In Fig. 10.66 the input transistors are degenerated to improve the accuracy and linearity. This was already described in Fig. 9.11. The resistors also give a standard way to calibrate the source resistors, and thereby the gain.

If we need to improve the accuracy and linearity more, the transistor parameters like G_m and voltage gain have to be increased by using a combination of transistors. In this way the transfer is accurately determined by the degeneration resistors and the transistor parameters fall out of the equations. Figure 10.67 shows how we can design an input stage that has compound P transistors and of which the input CM range includes the negative supply rail voltage V_SN. M₁₁ and M₁₂ are the input transistors. Their drain current is kept constant by M₁₃ and M₁₄. These transistors take on the current needed to drive the degeneration resistors R₁₁ and R₁₂ and feed that current to the output load resistors R31 and R₃₂. M₁₅ and M₁₆ are folded cascodes to allow the input voltage include the negative rail voltage V_SN [18]. A disadvantage of this circuit is that the current over square noise ratio is roughly 8–16 times worse than that of a simple differential input pair.

Figure 10.68 shows an accurate input N transconductance which input CM range includes the positive supply voltage V_SP. It has the same functionality as the circuit of Fig. 10.67 [16].

We must keep in mind that these degenerated input transconductances result in a roughly 8–16 times higher supply current over square voltage-noise ratio than the basic differential pair of Fig. 10.64 with transistors biased in weak inversion. The reason is that the current has to be split into several sources and transistors, each of which contribute to noise, and that the G_m is lowered by degeneration.

In the following three examples of dynamic element matching (DEM) it will be shown how the accuracy and linearity of instrumentation amplifiers is improved with only a small penalty on higher supply power over square noise voltage.

The ping-pong-pang auto-zero InstAmp of Fig. 10.16 can be provided with an auto-gain calibration, as shown in Fig. 10.69. The circuit has three input stages of which at any moment sequentially two stages are used to compose the feedback InstAmp topology, while the “third” stage is being, firstly, auto-zero trimmed and, secondly, auto-gain trimmed. The auto-zero offset trim has been explained at Fig. 10.16. The auto-gain trim can be done in many ways. In Fig. 10.69 the “third” stage in its calibration phase is connected at its input to a calibration voltage V_Cal2, while its output current is compared to a current from a calibration stage G_m24. That stage is also connected at its input to the calibration voltage V_Cal2. The current difference between the outputs of G_m23 and G_m24 is integrated and stored on C_Cal3. The voltage on C_Cal3 is used to calibrate the transconductance of G_m23 by controlling its tail bias current. In a next phase one of the other amplifiers is being calibrated and G_m23 is being used as one of the input amplifiers of the InstAmp. Each input stage has its own storage capacitor for its gain trim.

An important advantage of the combination of auto-zero and auto-gain is that the nonlinear transconductances of the input stages are more accurately equalized than if these stages were only auto-zeroed. This leads to low inaccuracies, in the order of 10⁻⁴, and also to low nonlinearities, in the order of 10⁻⁴.

In the same way the chopper instrumentation amplifier with ping-pong-pang auto-zero input stages of Fig. 10.24 can be auto-gain calibrated. This leads to an accurate and low-ripple auto-zero chopper instrumentation amplifier . This has not been shown separately.

The chopper-Stabilized InstAmp with auto-zeroed sense amplifiers of Fig. 10.32 can also be provided with auto-gain calibration [22]. This circuit is sketched in Fig. 10.70.

Calibration of the two offset sense amplifiers G_m51 and G_m52 needs only to result in the equality of these two amplifiers. This means that in the auto-calibration phase both inputs can simply be connected to a calibration voltage V_Cal and that the output currents can be compared. The difference of the output currents is being integrated and stored on a capacitor C_Cal. The voltage on the store capacitor controls through G_m53 the difference of the tail bias currents and thus the difference of the transconductances. At a large control loop gain the transconductances of G_m51 and G_m52 become equal. The auto-zero and auto-calibration can be placed in one main auto-correction phase.

We have to keep in mind that with chopper-stabilized instrumentation amplifiers the stabilization loop accurately controls the gain at low frequencies. At high frequencies the gain is set by differences in the main amplifier input stages , which are not auto-calibrated. Normally, this is not a problem because at high frequencies the gain is not accurate anyway because of lack in overall loop gain.

In the above example the auto-gain calibration was done in a time-discrete way. A time-continuous way to achieve a high accuracy and remove differences in the two input G_m’s of a chopper instrumentation amplifier can be obtained by applying dynamic-element matching (DEM) of the two input stages. To that purpose the two input stages are chopped back and forth between input and feedback. As a result of nonequal gains of the input stages an output ripple will arise at the frequency by which we interchange the input stages. If we DEM the input stages, for instance, at half the chopper frequency, a ripple will occur at the output at half the chopper frequency. This gain-error ripple can be reduced by a gain-error reduction loop (GERL) [21] independently of the offset RRL, which runs at the full clock frequency, as in the chopper InstAmp of Fig. 10.39a of the previous paragraph. The resulting circuit is shown in Fig. 10.71.

The gain-error reduction loop is made up from the capacitors C_S41 and C_S42, which sense the output ripple, chopper Ch₄, integrator G_m6, and correction amplifier G_m5. The last one differentially corrects a small part (for instance 2 %) of the bias currents of the input G_m’s. The result is a multiplicative correction on the input signals. If the gain is too large because g_m21 is larger than g_m22, the output ripple is positive in regard to the clock for a positive input signal. But the output ripple will be negative in regard to the clock for a negative input signal. Both situations need a correction in the same direction. Therefore, a comparator C₇ is used to measure the output polarity. A chopper Ch₅ is inserted to multiply the sense signal by the output polarity.

This analog GERL can also be made up in a digital way by using an ADC after Ch₄, a digital integrator, followed by a DAC. That way the digital loop can be provided with long-term memory for the best gain setting in times that the signal is small, and measured when the signal is not so small.

If the CM voltage levels of the input and feedback output are different, the CM voltage levels of the input transistor pairs are alternatively chopped high and low. This has two side effects: Firstly, if the input stages have a G_m that depends on the CM voltage, this dependency is not taken away by the DEM action. Therefore, the overall gain is slightly depending on the difference of the input and feedback CM voltage level. Hence, it is very important to choose input stages with a highly CM-independent G_m, as described in the beginning of this paragraph. Secondly, parasitic capacitors between the back gates and ground will cause large CM current spikes in the input stages. When these CM current spikes are larger than the bias currents the signal transfer is hampered. To lower the CM current spikes, the back gates of the input transistors and the cascodes can be actively bootstrapped to their CM input levels by class-AB source followers [21].

10.11.1 Conclusion

The combination of automated offset and gain calibration leads to an accurate equalization of the nonlinear characteristics of the input stages. This results not only in a low offset, of the order of microvolts, but also in a low inaccuracy, of the order of 10⁻⁴, and moreover in a low nonlinearity, of the order of 10⁻⁴, as the curved G_m characteristics of input and feedback are accurately matched. The continuous-time chopping and calibration method of simple differential transistor pairs in weak inversion leads to the lowest ratio between supply current and the square input voltage noise.

10.12 Summary Low Offset

Table 10.1 gives an overview of the roughly estimated offset and ripple of the operational amplifiers in the Sects. 10.5–10.9.

Table 10.1 Summary of offset and ripple that can be obtained

Full size table

Chopping generally can reduce offset by a factor of 10,000. But the ripple stays equal to the offset without other measures. Auto-zeroing reduces the offset by a factor of 100–500, depending whether the AZ store capacitors are placed at the input or at the output. Further improvement can be obtained when we combine chopping and auto-zeroing. Abbreviations used in Table 10.1 are: AZ = auto-zeroing, N = nested, ChSt = chopper-stabilized, Ch = chopping.

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Faculty of Electrical Engineering Mathematics and Computer Sciences (EEMCS), Delft University of Technology, Delft, The Netherlands
Johan Huijsing

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Johan Huijsing
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Huijsing, J. (2017). Low-Noise and Low-Offset Operational and Instrumentation Amplifiers. In: Operational Amplifiers. Springer, Cham. https://doi.org/10.1007/978-3-319-28127-8_10

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DOI: https://doi.org/10.1007/978-3-319-28127-8_10
Published: 10 July 2016
Publisher Name: Springer, Cham
Print ISBN: 978-3-319-28126-1
Online ISBN: 978-3-319-28127-8
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