Skip to main content

RF Circuits

  • Chapter
  • First Online:
  • 1040 Accesses

Abstract

There are two types of high-frequency circuits. One is a wideband circuit covering DC to RF or microwave frequencies. The other is a narrowband circuit operating at RF or microwave frequencies. The former is broadbanded by feedback while the latter operates in open loop, but occasionally with local feedback. The former is also for wireline baseband systems such as fiber and networking, but the latter is mostly for wireless RF transceivers. The key RF circuit elements are low-noise amplifier (LNA), mixer, power amplifier, and voltage-controlled oscillator (VCO). Most performance parameters for RF circuits can be enhanced mostly by optimizing open-loop parameters, but system-level DC parameters such as offset, image, and spurious tone can be self-trimmed. The bottleneck in RF system designs is the mixer spurious-free dynamic range (SFDR) performance. RF systems can be configured using global feedback and IF quantization concepts, which facilitate the integration of on-chip wireless systems. RF circuit and system issues are referred to the mixer SFDR performance, and various design concepts such as static and dynamic mixer linearity, impedance matching, loaded Q and fractional spur are addressed for efficient RF system implementations.

This is a preview of subscription content, log in via an institution.

Buying options

Chapter
USD   29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD   84.99
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD   129.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD   109.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Learn about institutional subscriptions

References

  1. B. Song, CMOS RF circuits for data communications applications. IEEE J. Solid State Circuits 21, 310–317 (1986)

    Article  Google Scholar 

  2. F. Montaudon, R. Mina, S. Le Tual, L. Joet, D. Saias, R. Hossain, F. Sibille, C. Corre, V. Carrat, E. Chataigner, J. Lajoinie, S. Dedieu, F. Paillardet, E. Perea, A scalable 2.4-to-2.7GHz Wi-Fi/WiMAX discrete-time receiver in 65nm CMOS, ISSCC Dig. Tech. Papers, Feb. 2008, pp. 362–363

    Google Scholar 

  3. S. Lerstaveesin, M. Gupta, D. Kang, B. Song, A 48-860MHz CMOS low-IF direct conversion DTV tuner. IEEE J. Solid State Circuits 43, 2013–2024 (2008)

    Article  Google Scholar 

  4. T. Cho, D. Kang, C. Heng, B. Song, A 2.4GHz dual-mode 0.18μm CMOS transceiver for bluetooth and 802.11b. IEEE J. Solid State Circuits 39, 1916–1926 (2004)

    Article  Google Scholar 

  5. C. Lu, H. Wang, C. Peng, A. Goel, S. Son, P. Liang, A. Niknejad, H. Hwang, G. Chien, A 24.7dBm all-digital RF transmitter for multimode broadband applications in 40nm CMOS, ISSCC Dig. Tech. Papers, Feb. 2013, pp. 332–333

    Google Scholar 

  6. D. Chowdhury, S. Thyagarajan, L. Ye, E. Alon, A. Niknejad, Fully-integrated efficient CMOS inverse class-D power amplifier for digital polar transmitters. IEEE J. Solid State Circuits 47, 1113–1122 (2012)

    Article  Google Scholar 

  7. T. Sano, M. Mizokami, H. Matsui, K. Ueda, K. Shibata, K. Toyota, T. Saitou, H. Sato, K. Yahagi, Y. Hayashi, A 6.3mW BLE transceiver embedded RX image-rejection filter and TX harmonic-suppression filter reusing on-chip matching network, ISSCC Dig. Tech. Papers, Feb. 2015, pp. 240–241

    Google Scholar 

  8. M. Perrott, T. Tewksbury, C. Sodini, A 27-mW CMOS fractional-N synthesizer using digital compensation for 2.5-Mb/s GFSK modulation. IEEE J. Solid State Circuits 32, 2048–2060 (1997)

    Article  Google Scholar 

  9. W. Rhee, A. Ali, B. Song, A 1.1 GHz CMOS fractional-N frequency synthesizer with a 3-b 3rd-order delta-sigma modulator, ISSCC Dig. Tech. Papers, 2000, pp. 198–199

    Google Scholar 

  10. B. De Muer, M. Steyaert, On the analysis of delta-sigma fractional-N frequency synthesizers for high-spectral purity, IEEE Trans. Circuits Syst. II, Nov. 2003, pp. 784–793

    Google Scholar 

  11. S. Norsworthy, R. Schreier, G. Temes, Delta-Sigma Data Converters: Theory, Design, and Simulation (IEEE Press, New York, 1997)

    Google Scholar 

  12. B. De Muer, M. Steyaert, A CMOS monolithic delta-sigma-controlled fractional-N frequency synthesizer for DCS-1800. IEEE J. Solid State Circuits 37, 835–844 (2002)

    Article  Google Scholar 

  13. J. Craninckx, M. Steyaert, A fully integrated CMOS DCS-1800 frequency synthesizer. IEEE J. Solid State Circuits 33, 2054–2065 (1998)

    Article  MATH  Google Scholar 

  14. B. Miller, R. Conley, A multiple modulator fractional divider. IEEE Trans. Instrum. Meas. 40, 578–583 (1991)

    Article  Google Scholar 

  15. T. Riley, M. Copeland, T. Kwasniewski, Delta-sigma modulation in fractional-N frequency synthesis. IEEE J. Solid State Circuits 28, 553–559 (1993)

    Article  Google Scholar 

  16. G. Gillette, Digiphase synthesizer, in Proceedings of 23rd Annual Frequency Control Symposium, 1969, pp. 201–210

    Google Scholar 

  17. W. Rhee, A. Ali, An on-chip compensation technique in fractional-N frequency synthesis, in IEEE International Symposium on Circuits and Systems, 1999, pp. 363–366

    Google Scholar 

  18. I. Bietti, E. Ternporitil, G. Albasini, R. Castello, An UMTS SD fractional synthesizer with 200kHz bandwidth and -128dBc/Hz @1MHz using spurs compensation and linearization techniques, in IEEE Custom Integrated Circuits Conference, 2003, pp. 463–466

    Google Scholar 

  19. S. Meninger, M. Perrott, A fractional-N frequency synthesizer architecture utilizing a mismatch compensated PFD/DAC structure for reduced quantization-induced phase noise, in IEEE Transactions on Circuits and Systems II, Nov. 2003, pp. 839–849

    Google Scholar 

  20. S. Pamarti, L. Jansson, I. Galton, A wideband 2.4GHz delta-sigma fractional-N PLL with 1-Mb/s in-loop modulation, IEEE J. Solid State Circuits 39, 49–62 (2004)

    Google Scholar 

  21. Y. Dufour, Method and apparatus for performing fractional division charge compensation in a frequency synthesizer, U.S. patent 6 130 561 (2000)

    Google Scholar 

  22. Y. Koo et al., A fully integrated frequency synthesizer with charge-averaging charge pump and dual path loop filter fro PCS and cellular CDMA wireless systems, IEEE J. Solid State Circuits 37, 536–542 (2002)

    Google Scholar 

  23. S. Pellerano et al., A dual band frequency synthesizer for 802.11a/b/g with fractional spur averaging technique, ISSCC Dig. Tech. Papers, 2005, pp. 20–22

    Google Scholar 

  24. M. Gupta, B. Song, A 1.8GHz spur-cancelled fractional-N frequency synthesizer with LMS-based DAC gain calibration, ISSCC Dig. Tech. Papers, Feb. 2006, pp. 478–479

    Google Scholar 

  25. M. Gupta, B. Song, A 1.8GHz spur-cancelled fractional-N frequency synthesizer with LMS-based DAC gain calibration. IEEE J. Solid State Circuits 41, 2842–2851 (2006)

    Article  Google Scholar 

  26. S. Dasgupta et al., Sign-sign LMS convergence with independent stochastic inputs. IEEE Trans. Inf Theory 36, 197–201 (1990)

    Article  MathSciNet  MATH  Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Rights and permissions

Reprints and permissions

Copyright information

© 2016 Springer International Publishing Switzerland

About this chapter

Cite this chapter

Song, BS. (2016). RF Circuits. In: System-level Techniques for Analog Performance Enhancement. Springer, Cham. https://doi.org/10.1007/978-3-319-27921-3_6

Download citation

  • DOI: https://doi.org/10.1007/978-3-319-27921-3_6

  • Published:

  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-319-27919-0

  • Online ISBN: 978-3-319-27921-3

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics