Architectural Synthesis of Petri Nets
New methods of Petri net array-based architectural synthesis are presented. Methods are based on the parallel decomposition of control algorithm into concurrently working state machine subnets and structural decomposition of a digital system. Structural decomposition leads to realization of a logic circuit as a two-level structure, where the combinational circuit of the first level is responsible for firing of transitions, and the second level is a memory used for generation of micro-operations. The memory organization depends on selected architecture. State machine subnets are determined by colors. Places are encoded using minimal numbers of bits. Micro-operations assigned to places are written in memory. Such an approach allows modular organization of logic circuit where each block has strictly determined function and balanced usage of different kinds of resources available in modern FPGAs.
KeywordsDigital circuits synthesis FPGAs Logic controllers Petri nets
- 1.Adamski, M., & Węgrzyn, M. (2009). Petri nets mapping into reconfigurable logic controllers. Electronics and Telecommunications Quarterly, 55(2), 157–182.Google Scholar
- 2.Adamski, M., Węgrzyn, M., & Wolański, P. (1998). A VHDL based Approach to Logic Controllers Design. In Proceedings of International Conference Programmable Devices and Systems PDS’98 (pp. 9–16). Gliwice, Poland.Google Scholar
- 5.Brown, S., & Vernesic, Z. (2005). Fundamentals of digital logic with VHDL design (2nd ed.). New York: McGraw-Hill.Google Scholar
- 6.Bukowiec, A. (2009). Synthesis of finite state machines for FPGA devices based on architectural decomposition (Vol. 13). Lecture notes in control and computer science. Zielona Góra: University of Zielona Góra Press.Google Scholar
- 8.Bukowiec, A., & Adamski, M. (2012). Logic synthesis for FPGAs of interpreted Petri net with common operation memory. In Z. Bradáč, F. Bradáč, & F. Zezulka (Eds.), 11th IFAC/IEEE International Conference on Programmable Devices and Embedded Systems PDeS 2012 (pp. 57–62). IFAC-PapersOnLine. Brno, Czech Republic.Google Scholar
- 10.Bukowiec, A., & Adamski, M. (2012). Synthesis of Petri nets into FPGA with operation flexible memories. In Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits and Systems DDECS’12 (pp. 16–21). Tallinn, Estonia.Google Scholar
- 14.Gomes, L., Costa, A., Barros, J., & Lima, P. (2007). From Petri net models to VHDL implementation of digital controllers. In 33rd Annual Conference of the IEEE Industrial Electronics Society IECON’07 (pp. 94–99). Taipei, Taiwan: IEEE.Google Scholar
- 16.Karatkevich, A. (2007). Dynamic analysis of petri net-based discrete systems (Vol. 356). Lecture notes in control and information sciences. Berlin: Springer.Google Scholar
- 17.Karatkevich, A., & Wiśniewski, R. (2012). Computation of Petri nets covering by SM-components based on the graph theory. Przeglad Elektrotechniczny, 88(8), 141–144.Google Scholar
- 18.Khamis, A., Zydek, D., Borowik, G., & Naidu, D. S. (2013). Control system design based on modern embedded systems. In R. Moreno-Díaz, F. R. Pichler, & A. Quesada-Arencibia (Eds.), Computer aided systems theory - EUROCAST 2013 (Vol. 8112, pp. 491–498). Lecture notes in computer science. Berlin: Springer.Google Scholar
- 19.Latorre-Biel, J.-I., Jiménez-Macías, E., Pérez de la Parte, M., Blanco-Fernández, J., & Martínez-Cámara, E. (2014). Control of discrete event systems by means of discrete optimization and disjunctive colored PNs: Application to manufacturing facilities. Abstract and Applied Analysis, 2014, 821707.MathSciNetCrossRefGoogle Scholar
- 21.Łuba, T., Borowik, G., & Kraśniewski, A. (2009). Synthesis of finite state machines for implementation with programmable structures. Electronics and Telecommunications Quarterly, 55(2), 183–200.Google Scholar
- 24.Rawski, M., Borowik, G., Łuba, T., Tomaszewski, P., & Falkowski, B. (2010). Logic synthesis strategy for FPGAs with embedded memory blocks. Przeglad Elektrotechniczny, 86(11a), 94–101.Google Scholar
- 26.Stefanowicz, Ł., Adamski, M., & Wiśniewski, R. (2013). Application of an exact transversal hypergraph in selection of SM-components. In L. Camarinha-Matos, S. Tomic, & P. Graça (Eds.), Technological innovation for the internet of things (Vol. 394, pp. 250–257). IFIP advances in information and communication technology. Berlin: Springer.Google Scholar
- 27.Tkacz, J. (2007). State machine type colouring of Petri net by means of using a symbolic deduction method. Measurement Automation and Monitoring, 53(5), 120–122.Google Scholar
- 28.Węgrzyn, A. (2006). On decomposition of Petri net by means of coloring. In Proceedings of IEEE East-West Design & Test Workshop EWDTW’06 (pp. 407–413). Sochi, Russia.Google Scholar
- 29.Wiśniewski, R., Stefanowicz, Ł., Bukowiec, A., & Lipiński, J. (2014). Theoretical aspects of Petri nets decomposition based on invariants and hypergraphs. In J. J. Park, S.-C. Chen, J.-M. Gil, & N. Y. Yen (Eds.), Multimedia and ubiquitous engineering (Vol. 308, pp. 371–376). Lecture notes in electrical engineering. Berlin: Springer.Google Scholar
Open Access This chapter is licensed under the terms of the Creative Commons Attribution-NonCommercial 2.5 International License (http://creativecommons.org/licenses/by-nc/2.5/), which permits any noncommercial use, sharing, adaptation, distribution and reproduction in any medium or format, as long as you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license and indicate if changes were made.
The images or other third party material in this chapter are included in the chapter's Creative Commons license, unless indicated otherwise in a credit line to the material. If material is not included in the chapter's Creative Commons license and your intended use is not permitted by statutory regulation or exceeds the permitted use, you will need to obtain permission directly from the copyright holder.