Advertisement

Effective Partial Reconfiguration of Logic Controllers Implemented in FPGA Devices

  • Remigiusz WiśniewskiEmail author
  • Monika Wiśniewska
  • Marian Adamski
Chapter
Part of the Studies in Systems, Decision and Control book series (SSDC, volume 45)

Abstract

A method of partial reconfiguration of logic controllers implemented in FPGA is presented in the chapter. Only the control memory content is replaced while the rest of the system is not modified. The logic synthesis and implementation are performed only once. Therefore, such a realisation highly accelerates the whole prototyping process. The performed experiments showed that the original bit-stream that is sent to the FPGA can be reduced even over 500 times.

Keywords

Logic controllers Microprogrammed controllers Partial reconfiguration Memory Control unit Implementation Field Programmable Gate Arrays (FPGA) 

References

  1. 1.
    Adamski, M., Wiśniewska, M., Wiśniewski, R., & Stefanowicz, Ł. (2012). Application of hypergraphs to the reduction of the memory size in the microprogrammed controllers with address converter. Przeglad Elektrotechniczny, 88(8), 134–136.Google Scholar
  2. 2.
    Altera. (2008.) Altera devices website. California: Altera.Google Scholar
  3. 3.
    Altera. (2010). Increasing design functionality with partial and dynamic reconfiguration in 28-nm FPGAs. Altera.Google Scholar
  4. 4.
    Baranov, S. I. (1994). Logic synthesis for control automata. Boston, MA, USA: Kluwer Academic Publishers.CrossRefGoogle Scholar
  5. 5.
    Barkalov, A., & Titarenko, L. (2009). Logic synthesis for FSM-based control units (Vol. 53). Lecture Notes in Electrical Engineering Berlin: Springer.Google Scholar
  6. 6.
    Bazydło, G., & Adamski, M. (2011). Specification of UML 2.4 HSM and its computer based implementation by means of Verilog. Przeglad Elektrotechniczny, 87(11), 145–149.Google Scholar
  7. 7.
    Chair Brayton, R. K. (Ed.). (1993). Sequential circuit synthesis at the gate level, Ph. D thesis. Berkeley: University of California.Google Scholar
  8. 8.
    DeMicheli, G. (1994). Synthesis and optimization of digital circuits. New York: McGraw-Hill Higher Education.Google Scholar
  9. 9.
    Doligalski M. (2012). Behavioral specification diversification for logic controllers implemented in FPGA devices: Proceedings of the Annual FPGA Conference, FPGAworld’12 (pp. 6:1–6:5), New York, USA: ACM.Google Scholar
  10. 10.
    Gajski, D. (1996). Principles of digital design. Upper Saddle River, NJ: Prentice Hall.Google Scholar
  11. 11.
    Grobelna, I. (2011). Formal verification of embedded logic controller specification with computer deduction in temporal logic. Przeglad Elektrotechniczny, 87(12a), 47–50.Google Scholar
  12. 12.
    Łuba, T. (2005). Synthesis of logic devices. Warszawa: Warsaw University of Technology Press.zbMATHGoogle Scholar
  13. 13.
    Maxfield, C. (2004). The design warrior’s guide to FPGAs. Orlando, FL, USA: Academic Press Inc.Google Scholar
  14. 14.
    Milik, A., & Hrynkiewicz, E. (2012). Synthesis and implementation of reconfigurable PLC on FPGA platform. International Journal of Electronics and Telecommunications, 58(1), 85–94.CrossRefGoogle Scholar
  15. 15.
    Parnell, K., & Mehta, N. (2003). Programmable logic design quick start hand book. San Jose, CA, USA: Xilinx.Google Scholar
  16. 16.
    Rudell, R. L. (1989). Logic synthesis for VLSI design, Ph. D thesis. Berkeley, CA, USA: EECS Department, University of California.Google Scholar
  17. 17.
    Sentovich, E., Singh, K. J. Moon, C. W. Savoj, H. Brayton, R. K. & Sangiovanni-Vincentelli, A. L. Sequential circuit design using synthesis and optimization. In ICCD ’92: Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors (pp. 328–333), Washington, DC, USA, 1992. IEEE Computer Society.Google Scholar
  18. 18.
    Thomas, D., & Moorby, P. (2002). The Verilog hardware description language (5th ed.). Norwell, MA: Kluwer Academic Publishers.zbMATHGoogle Scholar
  19. 19.
    Wilkes, M. V. (1951). The best way to design an automatic calculating machine: in Manchester University Inaugural Conference (pp. 182–184), Manchester, UK.Google Scholar
  20. 20.
    Wiśniewski, R. (2009). Synthesis of compositional microprogram control units for programmable devices. Lecture Notes in Control and Computer Science, vol. 14. Zielona Góra: University of Zielona Góra Press.Google Scholar
  21. 21.
    Xilinx. (2004). Two flows for partial reconfiguration. XilinxGoogle Scholar
  22. 22.
    Xilinx. (2007). Virtex-II Pro and Virtex-II Pro X FGPA user guide. Xilinx.Google Scholar
  23. 23.
    Xilinx. (2010). Partial reconfiguration user guide. Xilinx.Google Scholar
  24. 24.
    Zwolinski, M. (2000). Digital system design with VHDL. Inc, Boston, MA, USA: Addison-Wesley Longman Publishing Co.Google Scholar

Copyright information

© Springer International Publishing Switzerland 2016

Open Access This chapter is licensed under the terms of the Creative Commons Attribution-NonCommercial 2.5 International License (http://creativecommons.org/licenses/by-nc/2.5/), which permits any noncommercial use, sharing, adaptation, distribution and reproduction in any medium or format, as long as you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license and indicate if changes were made.

The images or other third party material in this chapter are included in the chapter's Creative Commons license, unless indicated otherwise in a credit line to the material. If material is not included in the chapter's Creative Commons license and your intended use is not permitted by statutory regulation or exceeds the permitted use, you will need to obtain permission directly from the copyright holder.

Authors and Affiliations

  • Remigiusz Wiśniewski
    • 1
    Email author
  • Monika Wiśniewska
    • 1
  • Marian Adamski
    • 1
  1. 1.Faculty of Electrical Engineering, Computer Science and TelecommunicationsUniversity of Zielona GóraZielona GóraPoland

Personalised recommendations