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FPGAs for Software Programmers pp 23–47Cite as

High-Level Synthesis

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Abstract

The compilation of high-level languages, such as software programming languages, to FPGAs is of paramount importance for the mainstream adoption of FPGAs. An efficient compilation process will improve designer productivity and will make the use of FPGA technology viable for software programmers. When targeting the hardware resources provided by FPGAs, a compilation process usually requires a stage known as High-Level Synthesis (HLS) which is responsible for generating application specific hardware architectures from the input source code or from an intermediate representation of the input application. This chapter briefly describes HLS and its main processing stages. The chapter provides the indispensable knowledge for readers who want to follow the remaining chapters of this book.

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Notes

  1. 1.

    Since addition and multiplication are commutative operations, the operand order has been changed for some nodes to improve the graph layout.

  2. 2.

    The adder could also be executed by a combined adder/subtracter or by an integer ALU.

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Authors and Affiliations

  1. University of Porto, Faculty of Engineering, Porto, Portugal

    João M. P. Cardoso

  2. INESC-TEC, Porto, Portugal

    João M. P. Cardoso

  3. Osnabrück University of Applied Sciences, Osnabrück, Germany

    Markus Weinhardt

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  1. João M. P. Cardoso
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  2. Markus Weinhardt
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Correspondence to João M. P. Cardoso .

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  1. The University of Manchester, Manchester, United Kingdom

    Dirk Koch

  2. Erlangen-Nürnberg, Friedrich-Alexander University, Erlangen, Germany

    Frank Hannig

  3. Dept. of Computer Science, Hardware/Software Co-Design, Erlangen, Germany

    Daniel Ziener

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Cardoso, J.M.P., Weinhardt, M. (2016). High-Level Synthesis. In: Koch, D., Hannig, F., Ziener, D. (eds) FPGAs for Software Programmers. Springer, Cham. https://doi.org/10.1007/978-3-319-26408-0_2

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