Riverside optimizing compiler for configurable computing (ROCCC) was started as a project at The University of California, Riverside in 2002. To put in a historical context: Field programmable gate arrays (FPGAs) were much smaller, and slower, then they are today (2015); Graphics processing units (GPUs) were used exclusively for graphics; reconfigurable computing was taking shape as a research area but not yet within the main stream of academic research, let alone in industrial production. However, multiple research projects had already demonstrated, many times over, the clear advantages and potentials of this nascent paradigm as an alternative that combines the re-programmability advantages of fixed data path devices (Central processing units (CPUs), Digital signal processors (DSPs) and GPUs) with the high speed of custom hardware (Application-specific integrated circuits (ASICs)). Within that time frame, the nearly exclusive focus of reconfigurable computing was on signal and image processing because of their streaming nature. Video processing was considered a future possibility to be realized when the size (area) and bandwidth capabilities of FPGAs got larger.
The development of ROCCC at UC Riverside was supported, in part, by NSF Grants CCF-0745490, CCF-0811416, CCF-0905509, IIS-1144158, IIS-1161997, CCF-1219180. The development of ROCCC 2.0 from the initial ROCCC toolset was carried out at Jacquard Computing Inc. supported by the US Air Force Research Lab contract FA945309C0173.
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