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ROCCC 2.0

  • Walid A. Najjar
  • Jason Villarreal
  • Robert J. Halstead
Chapter

Abstract

Riverside optimizing compiler for configurable computing (ROCCC) was started as a project at The University of California, Riverside in 2002. To put in a historical context: Field programmable gate arrays (FPGAs) were much smaller, and slower, then they are today (2015); Graphics processing units (GPUs) were used exclusively for graphics; reconfigurable computing was taking shape as a research area but not yet within the main stream of academic research, let alone in industrial production. However, multiple research projects had already demonstrated, many times over, the clear advantages and potentials of this nascent paradigm as an alternative that combines the re-programmability advantages of fixed data path devices (Central processing units (CPUs), Digital signal processors (DSPs) and GPUs) with the high speed of custom hardware (Application-specific integrated circuits (ASICs)). Within that time frame, the nearly exclusive focus of reconfigurable computing was on signal and image processing because of their streaming nature. Video processing was considered a future possibility to be realized when the size (area) and bandwidth capabilities of FPGAs got larger.

Notes

Acknowledgements

The development of ROCCC at UC Riverside was supported, in part, by NSF Grants CCF-0745490, CCF-0811416, CCF-0905509, IIS-1144158, IIS-1161997, CCF-1219180. The development of ROCCC 2.0 from the initial ROCCC toolset was carried out at Jacquard Computing Inc. supported by the US Air Force Research Lab contract FA945309C0173.

References

  1. [BCVN10]
    B. Buyukkurt, J. Cortes, J. Villarreal, and W. A. Najjar. Impact of high-level transformations within the ROCCC framework. ACM Trans. Archit. Code Optim., 7(4):17:1–17:36, December 2010.Google Scholar
  2. [Con15]
    Convey Computers. http://www.conveycomputer.com/, 2015. [Online; accessed 2-April].
  3. [FVLN15]
    E. Fernandez, J. Villarreal, S. Lonardi, and W. Najjar. FHAST: FPGA-based acceleration of Bowtie in hardware. Computational Biology and Bioinformatics, IEEE/ACM Transactions on, PP(99):1–1, 2015.Google Scholar
  4. [GBC+08]
    Z. Guo, A. Buyukkurt, J. Cortes, A. Mitra, and W. Najjart. A compiler intermediate representation for reconfigurable fabrics. International Journal of Parallel Programming (IJPP), 36(5):493–520, October 2008.Google Scholar
  5. [GBN04]
    Z. Guo, B. Buyukkurt, and W. Najjar. Input data reuse in compiling window operations onto reconfigurable hardware. In ACM SIGPLAN/SIGBED Conference on Languages, Compilers and Tools for Embedded Systems, pages 249–256, New York, NY, USA, June 2004. ACM Press.Google Scholar
  6. [GNB08]
    Z. Guo, W. Najjar, and B. Buyukkurt. Efficient hardware code generation for FPGAs. ACM Transaction on Architecture and Code Optimizations (TACO), 5(1):26, May 2008.Google Scholar
  7. [HANT15]
    R. J. Halstead, I. Absalyamov, W. A. Najjar, and V. J. Tsotras. FPGA-based multithreading for in-memory hash joins. In CIDR 2015, Seventh Biennial Conference on Innovative Data Systems Research, Asilomar, CA, USA, January 4-7, 2015, Online Proceedings, 2015.Google Scholar
  8. [HVN14]
    R. J. Halstead, J. R. Villarreal, and W. A. Najjar. Compiling irregular applications for reconfigurable systems. IJHPCN International Journal of High-Performance Computing and Networking, 7(4):258–268, 2014.CrossRefGoogle Scholar
  9. [LA04]
    C. Lattner and V. Adve. LLVM: A compilation framework for lifelong program analysis & transformation. In Proceedings of the International Symposium on Code Generation and Optimization: Feedback-directed and Runtime Optimization, CGO ’04, pages 75–88, Washington, DC, USA, 2004. IEEE Computer Society.Google Scholar
  10. [LLV15]
    LLVM. LLVM - Low Level Virtual Machine, 2015. http://www.llvm.org [Online; accessed 1-April].
  11. [NBD+03]
    W. A. Najjar, A. P. W. Böhm, B. A. Draper, J. Hammes, R. Rinker, J. R. Beveridge, M. Chawathe, and C. Ross. High-level language abstraction for reconfigurable computing. IEEE Computer, 36(8):63–69, 2003.CrossRefGoogle Scholar
  12. [WFW+94]
    R. P. Wilson, R. S. French, C. S. Wilson, S. P. Amarasinghe, J. M. Anderson, S. W. K. Tjiang, S.-W. Liao, C.-W. Tseng, M. W. Hall, M. S. Lam, and J. L. Hennessy. SUIF: An infrastructure for research on parallelizing and optimizing compilers. SIGPLAN Not., 29(12):31–37, December 1994.CrossRefGoogle Scholar

Copyright information

© Springer International Publishing Switzerland 2016

Authors and Affiliations

  • Walid A. Najjar
    • 1
  • Jason Villarreal
    • 1
  • Robert J. Halstead
    • 1
  1. 1.University of CaliforniaRiversideUSA

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