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On Switching Aware Synthesis for Combinational Circuits

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Hardware and Software: Verification and Testing (HVC 2015)

Part of the book series: Lecture Notes in Computer Science ((LNPSE,volume 9434))

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Abstract

We propose a synthesis algorithm for combinational circuits which optimizes the expected number of gate switchings induced by typical sequences of input vectors. Our algorithm, which is based on simple observations concerning AND gates, performs quite well on sequences produced by the same probabilistic models used to generate the training sequences.

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Author information

Authors and Affiliations

  1. VERIMAG CNRS and University of Grenoble, Grenoble, France

    Jan Lanik & Oded Maler

Authors
  1. Jan Lanik
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  2. Oded Maler
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Corresponding author

Correspondence to Jan Lanik .

Editor information

Editors and Affiliations

  1. University of Leicester, Leicester, United Kingdom

    Nir Piterman

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© 2015 Springer International Publishing Switzerland

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Lanik, J., Maler, O. (2015). On Switching Aware Synthesis for Combinational Circuits. In: Piterman, N. (eds) Hardware and Software: Verification and Testing. HVC 2015. Lecture Notes in Computer Science(), vol 9434. Springer, Cham. https://doi.org/10.1007/978-3-319-26287-1_17

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  • DOI: https://doi.org/10.1007/978-3-319-26287-1_17

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  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-319-26286-4

  • Online ISBN: 978-3-319-26287-1

  • eBook Packages: Computer ScienceComputer Science (R0)

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