Central Processing Unit

Abstract

This chapter is all about the design of a simple Reduced Instruction Set Computer (RISC) for central processing. The chapter starts with introducing simple assembly instructions and the required hardware to execute each instruction. But, it incrementally builds hardware around the initial hardware that can execute multiple instructions. Fixed-point and floating-point Arithmetic Logic Units (ALU) are studied in this chapter. Structural, data and program control hazards, and the required hardware to avoid them in a RISC Central Processing Unit (CPU) are also shown. This chapter ends with the operation of various cache architectures, cache read-and-write protocols, functionality of write-through and write-back caches.