Abstract
The chapter deals with design of Moore FSMs based on using embedded memory blocks. The methods of trivial EMB-based implementation of logic circuits of Moore FSMs are discussed. In this case, only a single EMB is enough for implementing the logic circuit. Next, the optimization methods are discussed based on the structural decomposition leading to two-level models of FSMs. It is shown how to use the classes of PES for decreasing the number of EMBs in the final circuit. The last section considers different methods proposed for diminishing the hardware amount in LUTer implementing the block of replacement of logical conditions. It is shown that at least 17 different models can be used for optimizing the LUTer.
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Barkalov, A., Titarenko, L., Kolopienczyk, M., Mielcarek, K., Bazydlo, G. (2016). Design of EMB-Based Moore FSMs. In: Logic Synthesis for FPGA-Based Finite State Machines. Studies in Systems, Decision and Control, vol 38. Springer, Cham. https://doi.org/10.1007/978-3-319-24202-6_8
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DOI: https://doi.org/10.1007/978-3-319-24202-6_8
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