Abstract
Chapter deals with optimization of logic circuits of Moore FSMs based on using two and three sources of codes of classes of pseudoequivalent states (PES). First of all, the application of this method for CPLD-based FSMs is discussed. Next, the models with two sources of class codes are discussed and corresponding design methods are proposed. This approach requires the usage of a multiplexor to choose a particular source. Also, the models with three sources of class codes are discussed and corresponding design methods are proposed. It is shown how the replacement of logical conditions can be used in multisource models of FSMs. At last, it is shown that the hardware reduction can be obtained due to increasing the number of class variables.
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Barkalov, A., Titarenko, L., Kolopienczyk, M., Mielcarek, K., Bazydlo, G. (2016). Distribution of Class Codes in Moore FSMs. In: Logic Synthesis for FPGA-Based Finite State Machines. Studies in Systems, Decision and Control, vol 38. Springer, Cham. https://doi.org/10.1007/978-3-319-24202-6_5
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DOI: https://doi.org/10.1007/978-3-319-24202-6_5
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