Skip to main content
SpringerLink
Log in

The Reconfigurable Cell Array

  • Chapter
  • First Online:
Book cover Heterogeneous Reconfigurable Processors for Real-Time Baseband Processing

  • 645 Accesses

Abstract

Emerging as a prominent technology, reconfigurable architectures have the potential of combining high hardware flexibility with high performance data processing. Conventional fine-grained architectures, such as Field-programmable gate arrays (FPGAs), provide great flexibility by allowing bit-level manipulations in system designs. However, the fine-grained configurability results in long configuration time and poor area and power efficiency, and thus restricts the usage of such architectures in time-critical and area/power-limited applications. To address these issues, recent work focuses on coarse-grained architectures, aiming to provide a balance between flexibility and hardware efficiency by adopting word-level data processing. In this chapter, a coarse-grained dynamically reconfigurable cell array architecture is introduced. The architecture is constructed from an array of heterogeneous functional units communicating via hierarchical network interconnects. The strength of the architecture lies in simplified data sharing achieved by decoupled processing and memory cells, substantial communication cost reduction obtained by a hierarchical network structure, and fast context switching enabled by a unique run-time reconfiguration mechanism. The presented reconfigurable cell array serves as a baseline architecture for two case studies presented in Chaps. 5 and 6.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Log in via an institution
Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 39.99
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Hardcover Book
USD 54.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

References

  1. Z. Abdin, B. Svensson, Evolution in architectures and programming methodologies of coarse-grained reconfigurable computing. Microprocessors Microsyst. Embed. Hardw. Des. 33, 161–178 (2009)

    Article  Google Scholar 

  2. R. Airoldi, F. Garzia, O. Anjum, J. Nurmi, Homogeneous MPSoC as baseband signal processing engine for OFDM systems. in International Symposium on System on Chip (SoC), Sept 2010, pp. 26–30

    Google Scholar 

  3. AMBA 4 AXI4-Stream Protocol Specification v1.0, Mar 2010

    Google Scholar 

  4. R. Baines, D. Pulley, A total cost approach to evaluating different reconfigurable architectures for baseband processing in wireless receivers. IEEE Commun. Mag. 41(1), 105–113 (2003)

    Article  Google Scholar 

  5. V. Baumgarte, G. Ehlers, F. May, A. Nückel, M. Vorbach, M. Weinhardt, PACT XPP-a self-reconfigurable data processing architecture. J. Supercomput. 26, 167–184 (2003)

    Article  MATH  Google Scholar 

  6. C. Bernard, F. Clermidy, A low-power VLIW processor for 3GPP-LTE complex numbers processing, in Design, Automation Test in Europe Conference Exhibition (DATE), Mar 2011, pp. 1–6

    Google Scholar 

  7. T. Bjerregaard, S. Mahadevan, A survey of research and practices of network-on-chip. ACM Comput. Surv. 38(1), 1 (2006)

    Google Scholar 

  8. B. Bougard, B. De Sutter, D. Verkest, L. Van der Perre, R. Lauwereins, A coarse-grained array accelerator for software-defined radio baseband processing. IEEE Micro 28(4), 41–50 (2008)

    Article  Google Scholar 

  9. J. Byrne, Tensilica DSP Targets LTE Advanced, Mar 2011. http://www.tensilica.com/uploads/pdf/MPR_BBE64.pdf

  10. A. Chattopadhyay, Ingredients of adaptability: a survey of reconfigurable processors, in VLSI Design, Jan 2013

    Google Scholar 

  11. F. Clermidy, et al., A 477mW NoC-Based Digital Baseband for MIMO 4G SDR. in IEEE International Solid-State Circuits Conference (ISSCC), Feb 2010, pp. 278–279

    Google Scholar 

  12. K. Compton, S. Hauck, Reconfigurable computing: a survey of systems and software. ACM Comput. Surv. 34, 171–210 (2002)

    Article  Google Scholar 

  13. M. Coppola, R. Locatelli, G. Maruccia, L. Pieralisi, A. Scandurra, Spidergon: a novel on-chip communication network, in International Symposium on System-on-Chip, 2004, p. 15

    Google Scholar 

  14. M. Dillinger, K. Madani, N. Alonistioti, Software Defined Radio: Architectures, Systems and Functions, 1st edn. (Wiley, New York, 2003)

    Google Scholar 

  15. A.Y. Dogan, J. Constantin, M. Ruggiero, A. Burg, D. Atienza, Multi-core architecture design for ultra-low-power wearable health monitoring systems, in Design, Automation Test in Europe Conference Exhibition (DATE), 2012, pp. 988–993

    Google Scholar 

  16. J. Eker, J.W. Janneck, CAL language report: specification of the CAL actor language. Technical Report, University of California at Berkeley, Nov 2003

    Google Scholar 

  17. R. Fasthuber, et al., Exploration of Soft-Output MIMO detector implementations on Massive parallel processors. J. Signal Process. Syst. 64, 75–92 (2011)

    Article  Google Scholar 

  18. R. Hartenstein, A decade of reconfigurable computing: a visionary retrospective, in Design, Automation Test in Europe Conference Exhibition (DATE), 2001, pp. 642–649

    Google Scholar 

  19. J. Janhunen, T. Pitkanen, O. Silven, M. Juntti, Fixed- and floating-point processor comparison for MIMO-OFDM detector. IEEE J. Sel. Top. Sign. Proces. 5(8), 1588–1598 (2011)

    Article  Google Scholar 

  20. G. Kahn, The semantics of a simple language for parallel programming, in Information Processing (North-Holland Publishing Company, Amsterdam, 1974), pp. 471–475

    Google Scholar 

  21. H. Lee, C. Chakrabarti, T. Mudge, A low-power DSP for wireless communications. IEEE Trans. Very Large Scale Integr. VLSI Syst. 18(9), 1310–1322 (2010)

    Article  Google Scholar 

  22. T. Lenart, Design of reconfigurable hardware architectures for real-time applications. Ph.D. thesis, Department of Electrical and Information Technology, Lund University, May 2008

    Google Scholar 

  23. Y. Lin, et al., SODA: a low-power architecture for software radio, in International Symposium on Computer Architecture (ISCA), 2006, pp. 89–101

    Google Scholar 

  24. A. Nilsson, E. Tell, D. Liu, An 11 mm2, 70 mW fully programmable baseband processor for mobile WiMAX and DVB-T/H in 0.12μm CMOS. IEEE J. Solid State Circuits 44(1), 90–97 (2009)

    Google Scholar 

  25. A. Nilsson, Design of programmable multi-standard baseband processors. Ph.D. thesis, Department of Electrical Engineering, Linköping University, 2007

    Google Scholar 

  26. R.S. Patti, Three-dimensional integrated circuits and the future of system-on-chip designs. Proc. IEEE 94(6), 1214–1224 (2006)

    Article  Google Scholar 

  27. B. Plunkett, J. Watson, Adapt2400 ACM architecture overview. Quicksilver, 2004. A Technology White Paper

    Google Scholar 

  28. A. Rahimi, I. Loi, M. R. Kakoee, L. Benini, A fully-synthesizable single-cycle interconnection network for shared-L1 processor clusters, in Design, Automation Test in Europe Conference Exhibition (DATE), 2011, pp. 1–6

    Google Scholar 

  29. M.A. Shami, A. Hemani, Morphable DPU: smart and efficient data path for signal processing applications, in IEEE Workshop on Signal Processing Systems (SiPS), Oct 2009, pp. 167–172

    Google Scholar 

  30. M.A. Shami, A. Hemani, Classification of massively parallel computer architectures, in IEEE 26th International Parallel and Distributed Processing Symposium Workshops PhD Forum (IPDPSW), May 2012, pp. 344–351

    Google Scholar 

  31. H. Svensson, T. Lenart, V. Öwall, Modelling and exploration of a reconfigurable array using systemC TLM, in IEEE International Symposium on Parallel and Distributed Processing, Apr 2008, pp. 1–8

    Google Scholar 

  32. H. Svensson, Reconfigurable architectures for embedded systems. Ph.D. thesis, Department of Electrical and Information Technology, Lund University, Oct 2008

    Google Scholar 

  33. M.B. Taylor, et al., A 16-issue multiple-program-counter microprocessor with point-to-point scalar operand network, in IEEE International Solid-State Circuits Conference, vol.1, Feb 2003, pp. 170–171

    Google Scholar 

  34. M. Thuresson, et al., FlexCore: utilizing exposed datapath control for efficient computing. J. Signal Process. Syst. 57(1), 5–19 (2009)

    Article  Google Scholar 

  35. T.J. Todman, G.A. Constantinides, S.J.E. Wilton, O. Mencer, W. Luk, P.Y.K. Cheung, Reconfigurable computing: architectures and design methods. Comput. Digit. Tech. 152, 193–207 (2005)

    Article  Google Scholar 

  36. K. van Berkel, F. Heinle, P.P.E. Meuwissen, K. Moerman, M. Weiss, Vector processing as an enabler for software-defined radio in handheld devices. EURASIP J. Appl. Signal Process. 2005, 2613–2625 (2005)

    Article  Google Scholar 

  37. Z. Yu, B.M. Baas, A low-area multi-link interconnect architecture for GALS chip multiprocessors. IEEE Trans. Very Large Scale Integr. VLSI Syst. 18(5), 750–762 (2010)

    Article  Google Scholar 

  38. C. Zhang, T. Lenart, H. Svensson, V. Öwall, Design of coarse-grained dynamically reconfigurable architecture for DSP applications, in International Conference on Reconfigurable Computing and FPGAs (ReConFig), Dec 2009, pp. 338–343

    Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Department of Electrical and Information Technology, Lund University, Lund, Sweden

    Chenxin Zhang, Liang Liu & Viktor Öwall

Authors
  1. Chenxin Zhang
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Liang Liu
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Viktor Öwall
    View author publications

    You can also search for this author in PubMed Google Scholar

Rights and permissions

Reprints and permissions

Copyright information

© 2016 Springer International Publishing Switzerland

About this chapter

Cite this chapter

Zhang, C., Liu, L., Öwall, V. (2016). The Reconfigurable Cell Array. In: Heterogeneous Reconfigurable Processors for Real-Time Baseband Processing. Springer, Cham. https://doi.org/10.1007/978-3-319-24004-6_4

Download citation

  • DOI: https://doi.org/10.1007/978-3-319-24004-6_4

  • Published:

  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-319-24002-2

  • Online ISBN: 978-3-319-24004-6

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics

Search

Navigation