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Scalable Digital CMOS Architecture for Spike Based Supervised Learning

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Engineering Applications of Neural Networks (EANN 2015)

Part of the book series: Communications in Computer and Information Science ((CCIS,volume 517))

Abstract

Supervised learning algorithm for Spiking Neural Networks (SNN) based on Remote Supervised Method (ReSuMe) uses spike timing dependent plasticity (STDP) to adjust the synaptic weights. In this work, we present an optimal network configuration amenable to digital CMOS implementation and show that just 5 bits of resolution for the synaptic weights is sufficient to achieve fast convergence. We estimate that the implementation of this optimal network architecture in \(65\,\)nm and a futuristic \(10\,\)nm digital CMOS could result in systems with close to 0.85 and 30 Million Synaptic Updates Per Second (MSUPS)/Watt.

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Author information

Authors and Affiliations

  1. Department of Electrical Engineering, IIT Bombay, Mumbai, India

    Shruti R. Kulkarni & Bipin Rajendran

Authors
  1. Shruti R. Kulkarni
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  2. Bipin Rajendran
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Corresponding author

Correspondence to Bipin Rajendran .

Editor information

Editors and Affiliations

  1. Democritus University of Thrace, Orestiada, Greece

    Lazaros Iliadis

  2. Coventry University, Coventry, United Kingdom

    Chrisina Jayne

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Kulkarni, S.R., Rajendran, B. (2015). Scalable Digital CMOS Architecture for Spike Based Supervised Learning. In: Iliadis, L., Jayne, C. (eds) Engineering Applications of Neural Networks. EANN 2015. Communications in Computer and Information Science, vol 517. Springer, Cham. https://doi.org/10.1007/978-3-319-23983-5_15

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  • DOI: https://doi.org/10.1007/978-3-319-23983-5_15

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  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-319-23981-1

  • Online ISBN: 978-3-319-23983-5

  • eBook Packages: Computer ScienceComputer Science (R0)

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